A dynamically reconfigurable wavefront array architecture for evaluation of expressions

Hartenstein, Reiner W.; Kress, Rainer; Reinig, Helmut

doi:10.1109/asap.1994.331785

Cited by 12 publications

(10 citation statements)

References 6 publications

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“…They devised a scalable and effective fashion to directly support the dataflow computational model and have been revived by some reconfigurable architectures (e.g., KressArray [6]). The dataflow computing model has been used in signal processing and other applications.…”

Section: Introductionmentioning

confidence: 99%

“…Some of them mix concepts of datadriven arrays with the reconfiguration properties of the programmable logic devices (e.g., FPGAs). Two such examples are the KressArray [6] and the XPP [11]. Although using coarse-grained architectures significant speedups have been achieved, the capability to compile from a high-level imperative programming language, and to still achieving noticeable speedup impact, has not been fully proved, apart from results on mapping specific algorithms.…”

Section: Introductionmentioning

confidence: 99%

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Self-loop Pipelining and Reconfigurable Dataflow Arrays

Cardoso

2004

Lecture Notes in Computer Science

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Abstract. This paper presents some interesting concepts of static dataflow machines that can be used by reconfigurable computing architectures. We introduce some data-driven reconfigurable arrays and summarize techniques to map imperative software programs to those architectures, some of them being focus of current research work. In particular, we briefly present a novel technique for pipelining loops. Experiments with the technique confirm important improvements over the use of conventional loop pipelining. Hence, the technique proves to be an efficient approach to map loops to coarse-grained reconfigurable architectures employing a static dataflow computational model

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Self-loop Pipelining and Reconfigurable Dataflow Arrays

Cardoso

2004

Lecture Notes in Computer Science

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“…Another synthesis system of that kind came later with a user interface based on a hardware description language came to ASAP'89 [9]. Systolic arrays on reconfigurable computing platform was covered at ASAP'94 [10]. Even going a step further discussed at ASAP'95 and ASAP'96 means a systolic methodology for programming a data-stream-based general purpose processor [11,12].…”

Section: The History Of Systolic Arraysmentioning

confidence: 99%

The tunnel vision syndrome: Massively delaying progress

Hartenstein

2013

2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors

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Professor, IEEE fellow, SDPS fellow, FPL fellow, TU Kaiserslautern, Karlsruhe Institute of Technology (KIT), UnBIntroduction. Despite of acceleration factors by up to several orders of magnitude the FPGA share in the IC market is still below 2%. The multicore and supercomputing dilemma massively reduces programmer productivity and the progress of performance improvement. Predictions are warning that, if current trends continue, the total of all electricity bills spiraling out of control could have serious consequences for the overall affordability of computing. The progress in power-efficient high performance solutions, coming from a few isolated areas, is by far too slow to break current trends. A few "silver bullet results" touting a single facet as the complete answer are far from solving the problem. What is the reason of these slow-down effects? Here the ASAP conference series was always a platform for critical discussions. The following sections illustrate, how the recognition of systolic arrays and term rewriting as fundamentals of datastream-based computing was delayed for decades by the tunnel vision syndrome.

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“…Some of the arrays use special horizontal and vertical connection resources (e.g., XPP). Others explicitly use PEs for routing and provide interconnections between PEs in a mesh (e.g., KressArray [17]) or in a hexagonal topology (e.g., [22]). …”

Section: Data-driven Array Architecturesmentioning

confidence: 99%

“…A number of coarse-grained architectures with dataflow semantics (e.g., KressArray [17], XPP [2], and WaveScalar [28]) have been focus of recent academic and commercial efforts, with encouraging results. They resemble many of the concepts of processor arrays, introduced in the 80's [31] [12], namely wavefront [23] and data-driven arrays [22].…”

Section: Introductionmentioning

confidence: 99%

Dynamic loop pipelining in data-driven architectures

Cardoso

2005

Proceedings of the 2nd Conference on Computing Frontiers

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Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable computing platforms. Their use has provided performance improvements over microprocessors and shorter programming cycles than FPGA-based platforms. As with other architectures, in data-driven architectures loop pipelining plays an important role to improve performance. Usually this kind of pipelining can be achieved using the dataflow software pipelining technique or other software pipelining approaches. Although performance improvements are achieved, those techniques heavily depend on the insertion of pipelining stages and thus require complex balancing efforts. Furthermore, those techniques statically define the pipelining and do not take fully advantage of the dynamic scheduling attainable by the datadriven concept. This paper presents a novel scheme to pipeline loops in data-driven architectures, orchestrated by a handshaking protocol. Using the new approach, self loop pipelining is naturally achieved. The scheme is based on duplicating cyclic hardware structures, in order they are autonomously executed, with synchronization being achieved by the data flow. It can be applied to nested loops, requires less aggressive pipeline balancing efforts than usual software pipelining techniques, and innermost loops with conditional structures can be pipelined without conservative pipelining implementations.We show results of using the proposed technique when mapping algorithms in imperative programming languages to the PACT eXtreme Processing Platform (XPP). The results confirm improvements over the use of conventional loop pipelining techniques. Better performance and fewer resources are achieved in a number of cases.

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A dynamically reconfigurable wavefront array architecture for evaluation of expressions

Abstract: Abstract

Cited by 12 publications

References 6 publications

Self-loop Pipelining and Reconfigurable Dataflow Arrays

Self-loop Pipelining and Reconfigurable Dataflow Arrays

The tunnel vision syndrome: Massively delaying progress

Dynamic loop pipelining in data-driven architectures

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