A dynamically tunable memory hierarchy

Abstract

Abstract-The widespread use of repeaters in long wires creates the possibility of dynamically sizing regular on-chip structures. We present a tunable cache and translation lookaside buffer (TLB) hierarchy that leverages repeater insertion to dynamically trade off size for speed and power consumption on a per-application phase basis using a novel configuration management algorithm. In comparison to a conventional design that is fixed at a single design point targeted to the average application, the dynamically tunable cache and TLB hierarchy can be tailored to the needs of each application phase. The configuration algorithm dynamically detects phase changes and selects a configuration based on the application's ability to tolerate different hit and miss latencies in order to improve the memory energy-delay product. We evaluate the performance and energy consumption of our approach and project the effects of technology scaling trends on our design.Index Terms-High performance microprocessors, memory hierarchy, reconfigurable architectures, energy and performance of on-chip caches.

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy

“…Prior work on reconfigurable caches has been restricted to a single 2D die and to relatively small caches [3,34,47]. Some prior work [19,33,43] logically splits large cache capacity across cores at run-time and can be viewed as a form of reconfiguration.…”

“…Many proposals of 2D reconfigurable caches already exist in the literature: they allow low access times for small cache sizes but provide the flexibility to incorporate larger capacities at longer access times. The use of 3D and NUCA makes the design of a reconfigurable cache especially attractive: (i) the spare capacity on the third die does not intrude with the layout of the second die, nor does it steal capacity from other neighboring caches (as is commonly done in 2D reconfigurable caches [3,47]), (ii) since the cache is already partitioned into NUCA banks, the introduction of additional banks and delays does not greatly complicate the control logic, (iii) the use of a third dimension allows access time to grow less than linearly with capacity (another disadvantage of a 2D reconfigurable cache).…”

Scheduling threads for constructive cache sharing on CMPs

“…Reducing power consumption. Because constructive cache sharing reduces the amount of cache needed by multithreaded programs (by up to a factor of P ), it provides new opportunities to power down segments of the cache [25,4,41]. Consider, for example, a cache architecture that supports eight 1 MB on-chip caches that can be powered on or off as needed.…”

“…In contrast, Mergesort is not bounded by memory bandwidth and its performance improves with more cores. 4 When making a design choice in the CMP design space, a typical goal is to optimize the performance of a suite of benchmark applications (e.g. SPEC) measured by aggregate performance metrics.…”

Superoptimization of memory subsystems

“…Methods to change the size and associativity of a cache hierarchy dynamically have been explored [2,29] and the ability to disable various levels of a multi-level cache in the interest of reducing latency and reducing power consumption has been considered [5]. Finally, adjusting the size of cache lines dynamically to lower the cache miss rate has been considered [31].…”