A fair arbitration for Network-on-Chip routing with odd-even turn model

Liu, Lu; Zhu, Zhangming; Zhou, Di; Yang, Yintang

doi:10.1016/j.mejo.2017.04.002

Cited by 20 publications

(19 citation statements)

References 29 publications

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“…We introduce two methods: (1) static analysis and (2) dynamic simulation, to evaluate the perform of these OE [7], OE-Arbiter [8], LAXY [6] and OLBR.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…When the traffic from the central node is transferred to the NS region, this region will become congested. In NS region, to improve the number of candidate output path of the conventional OE routing method, OLBR router employs the Alterable Priority Arbitration (APA) [8] for the fair granting of packet transmission from all possible directions permitted by the OE turn model. APA applies the granting mechanism of FP arbiter under varied priorities instead of fixed order, while the pointer to adjust the priority order is optimized for alterable priority arbitration.…”

Section: Proposed Routing Methodsmentioning

confidence: 99%

“…Copyright c 2021 The Institute of Electronics, Information and Communication Engineers number of candidate paths of OE turn model, OE-Arbiter [8] proposes an alterable priority arbitration (APA) for the fair granting of packet transmission from all possible directions permitted by the OE turn model. By applying the APA as selection for permitted routing directions, more candidate paths are provided to relieve congestion, the packet latency is reduced and the network capacity is improved.…”

Section: Introductionmentioning

confidence: 99%

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Simple Oblivious Routing Method to Balance Load in Network-on-Chip

Cai

Xie

Wang

et al. 2021

IEICE Trans. Inf. & Syst.

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This letter presents an oblivious and load-balanced routing (OLBR) method without virtual channels for 2D mesh Network-on-chip (NoC). To balance the traffic load of network and avoid deadlock, OLBR divides network nodes into two regions, one region contains the nodes of east and west sides of NoC, in which packets are routed by odd-even turn rule with Y direction preference (OE-YX), and the remaining nodes are divided to the other region, in which packets are routed by odd-even turn rule with alterable priority arbitration (OE-APA). Simulation results show that OLBR's saturation throughput can be improved than related works by 11.73% and OLBR balances the traffic load over entire network.

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“…We introduce two methods: (1) static analysis and (2) dynamic simulation, to evaluate the perform of these OE [7], OE-Arbiter [8], LAXY [6] and OLBR.…”

Section: Simulation Resultsmentioning

confidence: 99%

Section: Proposed Routing Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Simple Oblivious Routing Method to Balance Load in Network-on-Chip

Cai

Xie

Wang

et al. 2021

IEICE Trans. Inf. & Syst.

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show abstract

“…By running specific scenarios, these tools help to determine channel and buffer sizing, project routing and switching techniques, assess communication performance, specify packet format, and avoid starvation caused by deadlocks. NoC simulation tools have been adopted academically and by the industry in the last years [3,4,5,6,7,8,9,10,11,12,13,14,15]. However, most of these tools present a complex interface and require extra runtime and knowledge when explored together with hardware simulation tools.…”

Section: Introductionmentioning

confidence: 99%

A Multi-Agent-Based Network-on-Chip Simulator

Lima

Adamatti

Brião

et al. 2021

JICS

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Integrated systems have incorporated a variety of functionalities within the same chip, requiring on-chip communication mainly based on the Network-on-Chip (NoC) design paradigm. Complex systems may impose strict requirements concerning performance, power and reliability. Thus, the choice of proper routing algorithms to the on-chip communication for NoCs merits special attention. To assist designers to adjust communication parameters, implement routing algorithms, and check system correctness, simulators become powerful and cost-effective solutions. This article explores Multi-Agent System to develop a high level abstraction NoC simulation environment. The simulator allows designers to evaluate routing algorithms, test alternative configurations and message formats. The simulation provides important measurementssuch as rate of utilization of routers, network contention and delay in sending messages. As a case study, the XY and WF routing algorithms were modeled and analyzed. Results highlight the pros and cons of each algorithm, and outline the simulator overall performance.

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“…Expressively, the routing scheme influences the performance of the NoC that defines the path of a packet transferred in network architecture. [3] - [5]. Furthermore, the present FPGA's interconnection structure has several shortcomings that poorly affect the performance, limited the FPGA speed, and maximize the communication protocol [6].…”

Section: Introductionmentioning

confidence: 99%

An Adaptive Arbitration Technique w ith 4x4 Mesh Topology f or Low Area a nd High Speed NOC Design

Salagala*,

Sharma,

Laxmanarayana

2020

IJITEE

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 Abstract: In recent days, On-Chip Communication is a major requirement in modern systems that produce efficient communication with less complexity and high throughput. Due to heavy traffic and increasing Network-On Chip (NoC) size, the routing algorithm produces poor performances. Normally, round-robin and matrix arbiters are used in NoC for high-speed switches. In this research work, three different types of arbiter algorithms are used such as priority algorithm, Time Division Multiplexed (TDM) algorithm, and Viterbi algorithm to improve the linearity of the NOC. Initially, the priority algorithm helps to minimize traffic congestion when the arbiter is in a busy mode. Second, the fairness and Quality of Service (QoS) of the NoC structure are analyzed by the TDM algorithm. Finally, the Viterbi algorithm based error prediction process is done in an NoC structure. Due to the usage of three proposed arbiter algorithms, the area of NoC can be reduced. The packet can be reached to the destination by using the arbitration process with less loss. In this research, the proposed methodology is called as Low Area-Fault-Tolerant Adaptive Arbitration based NoC architecture (LA-FTAA-NoC architecture). Finally, the Field Programmable Gate Array (FPGA) performance is evaluated such as LUT, flip flop, slices, and frequency in Spartan 6 hardware. In the proposed method, 2.42% of LUT, 3.1% of flip flop, and 8.63% of slices have reduced when compared to existing work.

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A fair arbitration for Network-on-Chip routing with odd-even turn model

Cited by 20 publications

References 29 publications

Simple Oblivious Routing Method to Balance Load in Network-on-Chip

Simple Oblivious Routing Method to Balance Load in Network-on-Chip

A Multi-Agent-Based Network-on-Chip Simulator

An Adaptive Arbitration Technique w ith 4x4 Mesh Topology f or Low Area a nd High Speed NOC Design

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