An ultra-low power dynamic comparator is proposed with low dynamic offset variation for successive approximation register (SAR) analogue-to-digital converter (ADC). Dynamic offset can be cancelled with the cascode current source. Moreover, the power consumption can be reduced because it has no power consumption during the reset phase. With body-driven technology and cross-coupled inverter, the positive feedback during the regeneration is enhanced, which reduces remarkably delay time. Simulation results in a 0.18 μm CMOS technology confirm the performance of the proposed comparator. It is shown that the fluctuation of the total offset voltage (mean + 3std) is 0.15 and 0.39 mV with common-mode voltage from 0.5V DD to V DD at supply 1.2 and 0.6 V through Monte Carlo simulation, respectively. Furthermore, the delay of the proposed structure can be decreased to 1.837 and 118.2 ns at supply voltages of 1.2 and 0.6 V, while the power consumption is only 18.6 μW and 144 nW, respectively.

A fault-tolerant odd-even (FTOE) turn model and load-balancing multi-router fault-tolerant (LBMF) routing method that do not use virtual channels for mesh network-on-chip (NoC) are presented. Applying FTOE rules and routing packets around faulty regions in advance, LBMF balances the load around the faulty regions, and then the fault-tolerant paths are shortened. Simulation results show that LBMF's network injection rate can be improved than related works by 25, 40% for 16 × 16 mesh and in the presence of 20 faults.

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谢瑞莲 1) , 焦继业 2) , 刘有耀 2) 1) (西安邮电大学计算机学院 西安 710061) 2) (西安邮电大学电子工程学院 西安 710061)