Ultra‐low power comparator with dynamic offset cancellation for SAR ADC

Abstract

An ultra-low power dynamic comparator is proposed with low dynamic offset variation for successive approximation register (SAR) analogue-to-digital converter (ADC). Dynamic offset can be cancelled with the cascode current source. Moreover, the power consumption can be reduced because it has no power consumption during the reset phase. With body-driven technology and cross-coupled inverter, the positive feedback during the regeneration is enhanced, which reduces remarkably delay time. Simulation results in a 0.18 μm CMOS technology confirm the performance of the proposed comparator. It is shown that the fluctuation of the total offset voltage (mean + 3std) is 0.15 and 0.39 mV with common-mode voltage from 0.5V DD to V DD at supply 1.2 and 0.6 V through Monte Carlo simulation, respectively. Furthermore, the delay of the proposed structure can be decreased to 1.837 and 118.2 ns at supply voltages of 1.2 and 0.6 V, while the power consumption is only 18.6 μW and 144 nW, respectively.

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