An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

Abstract

A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript. It employs the conventional architecture of common-mode current feedback with the modified gain booster topology to increase gain, slew rate, and reduced gain error from the conventional structure. Observation from the simulation results concludes that the modified structure using 24 transistors shows power dissipation of 362.29 μW in 90 nm CMOS technology by deploying a supply voltage of 0.7 V, which is a 70% reduction as compared to the usual common mode feedback (CMFD) structure. The symmetric slew rate of 839.99 V/µs for both charging and discharging is obtained, which is 173% more than the standard CMFD structure. A reduction of 0.61% in gain error is achieved through this architecture. A SPICE simulation tool based on 90 nm CMOS technology is employed for executing the Monte Carlo simulations. A brief comparison with earlier CMFD structures shows improved performance parameters in terms of power consumption and slew rate with the reduction in gain error.

Study and Realization of an Alarm System by Coded Laser Barrier Analyzed by the Wavelet Transform

“…Comparator is one of the most important components of analog integrated circuits [14] ,The receiving circuit relies on a practical amplifier that compares the voltages E+ and E-Fig. 6 Laser receiving circuit using comparator LM741…”

International Journal of Electronics and Telecommunications

“…The comparator and DAC are classified as an essential and significant component in analog to digital data converter circuits [26]. Comparator equipped with common-mode feedback (current) with gain boosting techniques (CMFD-GB) is utilized for designing the ADC architecture [17], [27]. Figure 4 capacitor count in the capacitor rail which in turn decrease the signal strength as it travel to the comparator input.…”

“…A reinvigorate advanced architecture of 8-bit ADC is proposed and endowed in this work. The proposed structure is simulated with the comparator employing gain boosting technique with common mode current feedback (CMFD-GB) [16], [17]. A residue amplifier is employed for improving the signal strength inside the segmented DAC capacitor rail [18].…”

“…For simplification figure3(b) illustrates the schematic of the 2-bit binary thermal decoder (BTD) circuit[25].The comparator and DAC are classified as an essential and significant component in analog to digital data converter circuits[26]. Comparator equipped with common-mode feedback (current) with gain boosting techniques (CMFD-GB) is utilized for designing the ADC architecture[17],[27]. Figure4(a)illustrates the entire construction of the comparator (CMFD-GB) structure employed in designing this proposed 8-bit ADC…”