Simple fault‐tolerant method to balance load in network‐on‐chip

Xie, Ruilian; Cai, Jian; Xin, Xin

doi:10.1049/el.2015.3150

Cited by 7 publications

(4 citation statements)

References 4 publications

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“…However, the sophisticated structures of the aforementioned techniques make the NoC design under the complex stress condition. The second group of techniques focus mainly on the load balance of the network, which includes exploring the adaptive routing algorithm [3][4] and runtime workload balance mechanism by managing PE [5]. These techniques make the network load distributed evenly and thus alleviate the network congestion effectively to a certain extent.…”

Section: Introductionmentioning

confidence: 99%

Task Decomposition Exploration of Image Processing Applications on FPGA-Based NoC

Pang¹,

Fresse²,

Yao³

2017

dtcse

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Abstract.As the key interconnection technique of System on Chip (SoC), Network on Chip (NoC) architecture is widely used in the high-throughput and low-latency image processing system designs. In addition to the bandwidth and latency, managing congestion resulted from imbalance network load is critical to improve the system performance. In this paper, one task decomposition exploration method on FPGA-based NoC is presented. According to different parallel properties of tasks of the application, subtask graphs are generated by taking advantage of different decomposition strategies. These subtask graphs are evaluated in timing latency and energy consumption based on FPGA-based NoC emulation platform. The experiments demonstrate that the proposed task decomposition exploration can help the designer select the most appropriate task decomposition scheme based on properties of the application to balance NoC net-work load and alleviate congestion.

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Section: Introductionmentioning

confidence: 99%

Task Decomposition Exploration of Image Processing Applications on FPGA-Based NoC

Pang¹,

Fresse²,

Yao³

2017

dtcse

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“…Virtual channels are mainly used in the faulttolerant routing method for avoiding deadlock [1], improving performance and tolerating faults, but they introduce the additional area and increase the complex control logic of the router. Another fault-tolerant routing method without virtual channels avoids deadlock by using turn model [2], decreasing hardware costs, but it lowers performance because of less adaptivity. So a fault-tolerant routing method should introduce fewer virtual channels and have more adaptivity that packets are delivered through multiple paths to destinations.…”

Section: Introductionmentioning

confidence: 99%

Low-Cost Adaptive and Fault-Tolerant Routing Method for 2D Network-on-Chip

Xie

Xin

Yang

2017

IEICE Trans. Inf. & Syst.

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SUMMARY This letter presents a Preferable Mad-y (PMad-y) turn model and Low-cost Adaptive and Fault-tolerant Routing (LAFR) method that use one and two virtual channels along the X and Y dimensions for 2D mesh Network-on-Chip (NoC). Applying PMad-y rules and using the link status of neighbor routers within 2-hops, LAFR can tolerate multiple faulty links and routers in more complicated faulty situations and impose the reliability of network without losing the performance of network. Simulation results show that LAFR achieves better saturation throughput (0.98% on average) than those of other fault-tolerant routing methods and maintains high reliability of more than 99.56% on average. For achieving 100% reliability of network, a Preferable LAFR (PLAFR) is proposed.

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“…锯齿拓扑 FDOR (FDOR jagged edges routing, FJE)算法 [14] 拓展了 FDOR 算法, 可支持锯齿拓扑结构 , 但是其逻辑复杂 . 二级优先的 DOR(two priority dimension order routing, TPDOR) 算法 [15] 拓展了 FDOR 算法, 支持 3 个 mesh 拓扑以任意方式连接成的拓扑结构的子网, 增加了可适用的不规则子网拓扑类型.…”

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“…为了解决上述问题, 本文采用区域拓扑模型识别不规则子网, 并且结合已有研究成果的容错奇偶 (fault-tolerant odd-even, FTOE) 转向模型 [16] , 提出了一种低开销的隔离路由算法(low-cost isolation routing algorithm, LIRA [7] 算法)和 TPDOR [15] 算法与之进行比较.…”

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