A family of user-programmable peripherals with a functional unit architecture

Shubat, A.; Trinh, Cuong; Zaliznyak, A. A.; Ziklik, A.; Roy, Abhinaba; Kazerounian, R.; Cedar, Y.; Eitan, B.

doi:10.1109/4.126539

Cited by 4 publications

(1 citation statement)

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“…This is primarily driven by applications like RISC processors, ASIC's [l] and memory intensive peripherals such as Programmable System Devices (PSD's) [2], all requiring a significant amount of integrated SRAM. Common industry approach for embedded applications uses a 6-Transistor (6-T) full-CMOS cell in densities ranging from 64-256Kb.…”

Section: Introductionmentioning

confidence: 99%

A bipolar load CMOS SRAM cell for embedded applications

Shubat¹,

Kazerounian²,

Irani³

et al. 1995

IEEE Electron Device Lett.

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This paper presents a new SRAM cell concept which offers cell scaling without requiring complicated, specialized processing technology. The proposed cell utilizes a bipolar transistor in an open-base (base is floating) configuration as a simple means of realizing a high impedance load element. The Bipolar Transistor Load (BTL) is designed such that its open base current (the holding current) is always large enough to compensate for the NMOS pull-down transistor leakage current. The load holding current and the pull-down transistor leakage current are based on the same physical mechanism, namely thermal generation, as a result the load exhibits current tracking properties over varying process and temperature conditions. The cell size is 72 IL m2 with typical 0.8 p m design rules, which is about a 60% reduction as compared to a standard 6-T full CMOS cell. The operating properties of the BTL cell were studied analytically and characterized experimentally. The BTL SRAM module can be easily integrated as part of any CMOS process with minimal additional processing steps.

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Section: Introductionmentioning

confidence: 99%