A 30-ns cycle time 4-Mb mask ROM

Sunaga, T.

doi:10.1109/4.328636

Cited by 6 publications

(4 citation statements)

References 5 publications

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“…In this architecture, ROM is used for the majority of the code, while the Flash can be used for the Patch Memory. In addition, we use a fully-associative lookup structure for the Patch Link In examining recent circuit implementation papers, we see that each ROM bit has an area of approximately 4f 2 [13] where f is the minimum feature size. Flash densities are between 8f 2 and 10f 2 [14].…”

Section: Pi-rom and Flash Area Tradeoffsmentioning

confidence: 99%

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Patchable instruction ROM architecture

Sherwood

Calder

2001

Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems - CASES '01

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Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and local memory. The design of these systems is driven by two conflicting goals, the need for reduced area and the need for rapid development times. The two current design options for instruction storage, ROM and Flash, are each highly optimized to one of these two goals but provide little compromise between them. ROM is used for highly area optimized instruction memory, although this comes at a price of lengthy integration time due to it's need to be correct before the chip is sent for fabrication. Flash is an alternative instruction memory that can significantly reduce the time to market by allowing embedded software to be upgraded after fabrication, meaning that software test and fabrication can be overlapped. Unfortunately Flash takes over a factor of 2 times the area of the equivalent ROM based storage.In this paper we present the Patchable Instruction ROM as an architecture for instruction storage that can provide the best of both worlds -reduced area and faster time to market. With area efficiency similar to a standard ROM and support for limited post fabrication software patching, Patchable Instruction ROM provides a new set of design points to consider when building embedded systems. For the programs we examine, we show that our hardware/software technique can achieve an area only 10% larger than ROM with only an 11% inflation in design time over a Flash based approach.

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Section: Pi-rom and Flash Area Tradeoffsmentioning

confidence: 99%

“…All three memory types are common VLSI structures with a high degree of regularity. We calculate area from recently publish work [13,14,11].…”

Section: Pi-rom and Flash Area Tradeoffsmentioning

confidence: 99%

Patchable instruction ROM architecture

Sherwood

Calder

2001

Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems - CASES '01

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“…Hence, the chip size and power consumption need to be enhanced, as well as the improvement of speed. Prior ROM designs were mainly focused on the technology evolution [1], [4], [6], core architecture [5], [7], or special-purpose circuit and logic [2], [3]. The improvement of address decoders and data encoding for ROMs has long been ignored.…”

Section: Introductionmentioning

confidence: 99%

An area-saving decoder structure for ROMs

Wang¹,

Hsueh²,

Chen³

2003

IEEE Trans. VLSI Syst.

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Read-only memories (ROMs) are widely used in both digital communication systems and daily consumer electronics. The major functions of ROMs are storage of data, programs, firmwares, etc. In this paper, a three-dimensional decoding structure for ROMs is proposed. The number of address decoding stages is drastically shortened. Hence, the delay is reduced, as well as the power consumption and area. The analysis of overall transistor count and delay is thoroughly derived. A real 256 8 ROM possessing the proposed decoder is physically fabricated by 0.5m two-poly two-metal (2P2M) CMOS technology.

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“…Instead of implanting ion to achieve multiple threshold voltages in some counterparts like the "flat cell" mask ROM [2] resulting in multi layer cell, this present design applies the principle of multiple channel widths and lengths thin field and poly gate programming. In the 0.18um CMOS standard process, due to the design rule, an N-type device with a minimum width and minimum length will have an area of 0.80um x 0.90um cell which has some waste space which is used to make 2 to 5 incremental of the channel width with 0.05um for each incremental step.…”

Section: Mlc Rom Cell Structurementioning

confidence: 99%

A Nor-Type MLC ROM with Novel Sensing Scheme for Embedded Applications

Sung¹,

Chang

Chen

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05)

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A 3 bits per cell Nor-type MLC ROM, Multi Layer Cell Read Only Memory macro of 4M bits density is presented. The MLC ROM is designed by a 0.18 um CMOS logic process. The ROM cell of 0.80um x 0.90um with 0.05um per step of the channel width and channel length increase is determined to obtain 16 levels of Ids. A novel scheme of 2-step sensing with current-to-voltage converter (Step1) and an ADC (step2) are applied to obtain an access time of 10 ns. I.

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A 30-ns cycle time 4-Mb mask ROM

Cited by 6 publications

References 5 publications

Patchable instruction ROM architecture

Patchable instruction ROM architecture

An area-saving decoder structure for ROMs

A Nor-Type MLC ROM with Novel Sensing Scheme for Embedded Applications

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