An area-saving decoder structure for ROMs

Wang, Chua-Chin; Hsueh, Ya-Hsin; Chen, Ying-Pei

doi:10.1109/tvlsi.2003.816134

Cited by 2 publications

References 6 publications

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Data dependent optimization of ROM structures

Vallapaneni¹,

Prasad

2009

2009 IEEE International Symposium on Circuits and Systems

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Fig. 1. (a) Conventional ROM structure (b) NMOS static NOR row address decoder and (c) 3-bit column mux using pass transistors memory into multiple banks, with each bank having fewer data bits [11]. This would definitely improve the collapsibility of word lines. For example, a 32x16 ROM can be organized as 4 banks, each of 32x4. In this structure, only a maximum of 16 word lines need to be generated for each bank. Equations to compute transistor counts and advantages of the proposed structure over the conventional structure are discussed in the subsequent sections. III. TRANSISTOR COUNT ANALYSISThe following analysis is valid, as long as the conventional and the proposed ROM structures use the same circuit design style. The word line : ; ------0 Data word lines " . '--_.----• • ROM core •••• •••• A A (c) (b) A AddressAbstract-Read Only Memories (ROMs) occupy 40% to 80% of the area in most of the current generation System on Chips (SoCs ). Hence, any reduction in ROM area could effectively result in chips with low die area. A novel optimized ROM structure based on data contents is proposed in this paper. Customized address decoder and memory core are designed based on data contents leading to an area reduction of up-to 60 % and considerable reduction in power and access times. Analysis of overall transistor count is performed for a few real-life SoC applications and also for random data.

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Data dependent optimization of ROM structures

Vallapaneni¹,

Prasad

2009

2009 IEEE International Symposium on Circuits and Systems

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Analysis and Reduction of Supply Noise Fluctuations Induced by Embedded Via-Programming ROM

Chang

Yang

2009

IEEE Trans. VLSI Syst.

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Various input addresses and accessed code-patterns of a via-programming read only memory (ROM) cause substantial fluctuations in peak current and supply noise across cycles. This work analyzes the fluctuations in the supply noise that are associated with the pattern-dependent current profile of embedded via-programming ROM on a QFN package with various decoupling capacitances. A pattern-insensitive (PI) technique is developed for via-programming ROM to reduce both fluctuations of peak current and cycle current across various input addresses and accessed code-patterns. The PI technique involves the arranging of the data patterns of a ROM-code and the adjustment of the structures of row decoders and peripheral circuits. Experiments based on the designed test-setup on fabricated 0.25 m 256 kb ROM macros demonstrate the fluctuation in peak current of conventional ROM and its reduction by the PI technique. The fluctuations of measured peak and cycle currents of PI-ROM are only 0.7% and 13.1% of those of conventional ROM. The PI-ROM also has a 94.5% lower standby current than conventional ROM.Index Terms-Code-patterns, peak current, read only memory (ROM), supply noise.

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An area-saving decoder structure for ROMs

Cited by 2 publications

References 6 publications

Data dependent optimization of ROM structures

Data dependent optimization of ROM structures

Analysis and Reduction of Supply Noise Fluctuations Induced by Embedded Via-Programming ROM

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