A Nor-Type MLC ROM with Novel Sensing Scheme for Embedded Applications

Abstract

A 3 bits per cell Nor-type MLC ROM, Multi Layer Cell Read Only Memory macro of 4M bits density is presented. The MLC ROM is designed by a 0.18 um CMOS logic process. The ROM cell of 0.80um x 0.90um with 0.05um per step of the channel width and channel length increase is determined to obtain 16 levels of Ids. A novel scheme of 2-step sensing with current-to-voltage converter (Step1) and an ADC (step2) are applied to obtain an access time of 10 ns. I.