No abstract

A 3 bits per cell Nor-type MLC ROM, Multi Layer Cell Read Only Memory macro of 4M bits density is presented. The MLC ROM is designed by a 0.18 um CMOS logic process. The ROM cell of 0.80um x 0.90um with 0.05um per step of the channel width and channel length increase is determined to obtain 16 levels of Ids. A novel scheme of 2-step sensing with current-to-voltage converter (Step1) and an ADC (step2) are applied to obtain an access time of 10 ns. I.

An LCD Driver with on-chip frame buffer and 3 times image compression codec reaching visually lossless image quality is presented. The frame buffer compression codec can encode and decode up to eight pixels in one clock cycle. Integrating a whole frame buffer with RGB=888 bits into the display driver sharply reduces power dissipated between the IO pad and PCB board at a cost of 50% IC die area increase. The existing working chip (STE2102, a ram-less LCD Driver with die size of 170mm x 12mm) is manufactured by ST Micro 0.18um high voltage CMOS process. A new chip design with on-chip frame buffer SRAM and 3 times compression codec supporting QVGA (320x240) is completed which reduces the frame buffer SRAM density and area by a factor of ~3.0 times and cuts the power consumption of the on-chip SRAM frame buffer by ~9.0 times of which 3 times is contributed by less capacitive bit line load and another 3 times from data rate reduction from image compression. The compression codec having 25K gates in encoder and 10K in decoder accepts both YUV and RGB color formats. An on-chip color-space-conversion unit converts the decompressed YUV components with 420, 422 and 444 formats to be RGB format before driving out to be displayed. The high image quality is achieved by applying some patented proprietary compression algorithms including accurate prediction in DPCM, a Golomb-Rice like VLC coding with accurate predictive divider and an intelligent bit rate distribution control.