The widespread usage of wide bandgap (WBG) semiconductors forces extra emphasis on the early estimation of the layout parasitic elements. Be it a printed circuit board or a power module, layout optimization is necessary to minimize the negative effects of present inductances. Unfortunately, multiple invocations of inductance extraction software can be timeconsuming. In this work, state-of-the-art convolutional neural networks (CNN) are applied in order to lower the time consumption of inductance estimation without compromising the accuracy.