A fast and accurate method of redesigning analog subcircuits for technology scaling

Funaba, Seiji; Kitagawa, Akihiro; Tsukada, T.; Yokomizo, Goichi

doi:10.1109/aspdac.1998.669532

Cited by 8 publications

(8 citation statements)

References 7 publications

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“…Optimization, although appealing, has very long run/debug times and the optimizer may easily produce improper designs if the right design constraints are not provided to the optimization problem. In [11], instead of optimizing on the circuit performance, optimization targeted the tolerances of the equivalent small-signal model component values of the source design. This limited simulations to fast operating-point analysis, which achieved a considerable enhancement in the total optimization CPU time.…”

Section: Circuit Migrationmentioning

confidence: 99%

Analog design migration: An overview

Dessouky¹

2009

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

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This paper presents an overview on automated analog design migration. Different approaches dedicated to design migration of both circuit and layout phases are discussed. It is shown that in order that a solution be accepted by the design community, it must reflect all design information, heuristics and choices made in the original design to the target design. A tool based on design extraction is presented in more details with a test case.

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Section: Circuit Migrationmentioning

confidence: 99%

Analog design migration: An overview

Dessouky¹

2009

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

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“…And it was also extended in [5], using a tuning procedure based on an optimization loop [6]. and [8] based their approaches on an optimization loop and intensive SPICE simulations in order to check and suitably modify circuit parameters to obtain the specified performances.…”

Section: State Of Artmentioning

confidence: 99%

Scaling guidelines for CMOS linear analog design

Levi

Lewis

Tomas

et al. 2007

2007 Ph.D Research in Microelectronics and Electronics Conference

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This paper proposes scaling guidelines for CMOS analog design during a technology migration. The scaling rules aim to be easy to apply and are based on the simplest MOS transistor model. The principle is to transpose one circuit topology from one technology to another, while keeping the main figures of merit, and the issue is to quickly calculate the new transistor dimensions. Furthermore, when the target technology has smaller minimum length, we expect to obtain a decrease of area. The proposed guidelines are applied to linear examples: OTAs. The results are compared on four CMOS processes whose minimum length are 0.8 μ μ μ μm, 0.35 μ μ μ μm, 0.25 μ μ μ μm and 0.12 μ μ μ μm.

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“…Hence, the automatic migration of analog circuits design is not a straightforward task as the digital counterpart and often involves the complete circuit redesign. Recently, in order to face this problem, several solutions were proposed both at research [1]- [3] and at commercial level [4]; the approaches [3] and [4] are based on optimization loops and massive SPICE simulations, solutions [1] and [2] are fully analytical approaches. In [5], the analytical approach of [1] and [2] defined for MOSFETs in the saturation region was generalized to account for transistors biased in the triode region.…”

Section: Introductionmentioning

confidence: 99%

Automatic Scaling Procedures for Analog Design Reuse

Savio

Colalongo

Quarantelli

et al. 2006

IEEE Trans. Circuits Syst. I

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In this paper, a methodology for analog design reuse is proposed. The basic idea is to keep the circuit topology unchanged while automatically modifying the MOSFETs aspect ratio in order to control the transistor transconductances gm and output conductances gDS. If gm’s and gDS’s of each transistor are kept unchanged through the scaling procedure, we show that the overall frequency behavior of the scaled circuit remains very similar to the original one. The approach is very simple and it is suitable for the scaling of analog circuits. No input and output terminals have to be defined and it can be straightforwardly implemented in an automatic scaling tool. When this approach fails, more complex iterative numerical loops may be adopted. In order to validate and compare the scaling approaches, several linear and nonlinear circuits were scaled from a 0.25-um, 2.5-V voltage supply to a 0.15-um, 1.2-V voltage supply in standard CMOS technologies

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A fast and accurate method of redesigning analog subcircuits for technology scaling

Cited by 8 publications

References 7 publications

Analog design migration: An overview

Analog design migration: An overview

Scaling guidelines for CMOS linear analog design

Automatic Scaling Procedures for Analog Design Reuse

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