A fast HDL model for full-custom FPGA verification

Zhang, Kaixuan; Feng, Zhihua; Zhou, Hao

doi:10.1109/asicon.2017.8252644

Cited by 4 publications

(2 citation statements)

References 2 publications

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“…Compared with the 256-bit bus width, 128-bit can save a lot of hardware resources and multi-bit calculation. To obtain a sufficiently large-scale CNN computing power, the change in the process leads to a decrease in computational reliability [11] . Table 4 compares the hardware resources consumed by the same type of accelerator and this design under the condition of keeping the same conditions as clock frequency, bus bit width, and the number of master-slave interfaces.…”

Section: Analysis Of Verification Resultsmentioning

confidence: 99%

Design and verification of convolutional neural network accelerator

Xiang

Sui

Zhang

2023

International Conference on Signal Processing, Computer Networks, and Communications (SPCNC 2022)

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The existing software implementation schemes of Convolutional Neural Networks (CNN) cannot meet the requirements of computing performance and power consumption. To further improve the energy efficiency of the deep neural network, improve throughput and reduce power consumption, a hardware accelerator based on a convolutional neural network was designed, and a verification platform was built for it. The platform has good reusability and can flexibly complete the verification work of the target chip under various modes and configurations, and perform performance evaluation and functional correctness verification on the chip. Through the board-level verification results, this design reduces power consumption by 12.36% compared with similar accelerators and improves hardware resource utilization by 13.87% while keeping the same conditions as clock frequency and bus bit width.

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Section: Analysis Of Verification Resultsmentioning

confidence: 99%

Design and verification of convolutional neural network accelerator

Xiang

Sui

Zhang

2023

International Conference on Signal Processing, Computer Networks, and Communications (SPCNC 2022)

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“…Another step was the evolution of tools such as MATLAB and Simulink, used frequently in electronic systems' mathematical modeling, which had dedicated toolboxes added, thus streamlining the hardware implementation of digital controllers associated with the system modeled. The latter could be electronic, electrical, and/or mechatronic, therefore bridging the gap between mathematical modeling and hardware prototyping tools, such as those based on microprocessor/DSP compilers or hardware description languages (HDLs) [6] and facilitating hardware implementation in field programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). Due to the increased availability of FPGAs, which contain microprocessor/DSP cores, as multi-million-gate digital and reconfigurable system-on-chip, design methods had to adapt to enable faster time-to-market for complex products.…”

Section: Brief Historical Evolution Of Electronic Systems Design Meth...mentioning

confidence: 99%

Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends

Cirstea,

Benkrid,

Dinu

et al. 2024

Micromachines

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This paper reviews the evolution of methodologies and tools for modeling, simulation, and design of digital electronic system-on-chip (SoC) implementations, with a focus on industrial electronics applications. Key technological, economic, and geopolitical trends are presented at the outset, before reviewing SoC design methodologies and tools. The fundamentals of SoC design flows are laid out. The paper then exposes the crucial role of the intellectual property (IP) industry in the relentless improvements in performance, power, area, and cost (PPAC) attributes of SoCs. High abstraction levels in design capture and increasingly automated design tools (e.g., for verification and validation, synthesis, place, and route) continue to push the boundaries. Aerospace and automotive domains are included as brief case studies. This paper also presents current and future trends in SoC design and implementation including the rising, evolution, and usage of machine learning (ML) and artificial intelligence (AI) algorithms, techniques, and tools, which promise even greater PPAC optimizations.

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Engineering Management Methods for FPGA Products in the Aviation and the Aerospace Fields

Xing¹,

Zhang³

2020

Lecture Notes in Electrical Engineering

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A fast HDL model for full-custom FPGA verification

Cited by 4 publications

References 2 publications

Design and verification of convolutional neural network accelerator

Design and verification of convolutional neural network accelerator

Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends

Engineering Management Methods for FPGA Products in the Aviation and the Aerospace Fields

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