A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment

Lin, Jung-Mao; Yang, Ching-Yuan

doi:10.1109/tcsi.2015.2477575

Cited by 41 publications

(26 citation statements)

References 28 publications

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“…A second-order analog PLL was used to analyze the frequency response of the ADPLL [39]. A proportionalintegral scheme was used in the DLF algorithm ( Fig.…”

Section: Architecture Of the Adpllmentioning

confidence: 99%

A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled Oscillator

Liu

2021

IEEE Access

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An all-digital phase-locked loop (ADPLL) with a multiphase digitally controlled oscillator (DCO) incorporating the bootstrapped and interpolated schemes is proposed in this paper. The bootstrapped ring oscillator can boost the output voltage to a higher level than the supply voltage. Thus, the oscillator can be operated in low-supply-voltage applications. MOS varactor is used in the bootstrapped capacitor to reduce the area cost. Circuit analysis and simulated verification were performed for an optimized design. The interpolated DCO has multiphase outputs and a high operating frequency. The test chip was implemented in a 90-nm CMOS process, and the core area was 60 × 117 μm 2. The power consumptions at 1160 MHz and 20 MHz were 912.6 μW (at 0.6 V) and 2.94 μW (at 0.2 V), respectively. In the worst-case jitter performance, the root mean square (RMS) jitters were less than 0.42%. INDEX TERMS Bootstrapped, digitally controlled oscillator (DCO), interpolation, multiphase, phaselocked loop (PLL).

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“…A second-order analog PLL was used to analyze the frequency response of the ADPLL [39]. A proportionalintegral scheme was used in the DLF algorithm ( Fig.…”

Section: Architecture Of the Adpllmentioning

confidence: 99%

A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled Oscillator

Liu

2021

IEEE Access

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“…As the figure shows, even if the differences between each pair of T A and T B is small, they will be stored and accumulated by FD, and the accumulation will become large enough to detect. Moreover, given that LSD's division factor is set to (M + 1) for n times and M for (N − n) times within N periods, according to (3) and (4), the final result can be expressed as:…”

Section: B the Averaged Fraction Division Schemementioning

confidence: 99%

An Intermittent Frequency Synthesizer With Accurate Frequency Detection for Fast Duty-Cycled Receivers

et al. 2020

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An intermittent frequency synthesizer for fast duty-cycled receivers is presented in this paper. Different from state-of-art techniques which try to eliminate the initial phase error that degrades the intermittent frequency detection, a new frequency detector is proposed to maintain an accurate frequency detection regardless of the initial phase error. Moreover, an averaged fraction division scheme (AFDS) is integrated in the synthesizer to improve the frequency resolution. The frequency synthesizer is implemented and verified by using discrete devices and an FPGA. The measurement results show that the frequency detector provides a frequency detection accuracy of 0.88%, and the synthesizer achieves a frequency resolution of 0.625 MHz when controlled by a duty-cycled signal with a 6-µs period and a 2-µs time duration. The frequency synthesizer can perform an intermittent frequency hopping from 160MHz to 140MHz while requiring a period of 430 µs without disturbing the VCO's oscillation.

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“…All Digital Phase Locked Loops (ADPLLs) are compulsory components in many microelectronic systems since they generate clocking signals. In recent applications, ADPLLs are interconnected into trees or networks to generate a synchronised distributed signal [1]- [9]. The research on ADPLLs and their networks is driven by the following major issues: how to ensure the synchronisation and stability of a single ADPLL or a network [10]- [15] and how to minimise their jitter [16]- [25].…”

Section: Introductionmentioning

confidence: 99%

Averaging Techniques for the Analysis of Event Driven Models of All Digital PLLs

Koskin

Galayko²,

Blokhina

2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

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A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment

Cited by 41 publications

References 28 publications

A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled Oscillator

A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled Oscillator

An Intermittent Frequency Synthesizer With Accurate Frequency Detection for Fast Duty-Cycled Receivers

Averaging Techniques for the Analysis of Event Driven Models of All Digital PLLs

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