A fast low-power modulo 2&lt;sup&gt;n&lt;/sup&gt;+1 multiplier design

Modugu, Rajashekhar; Choi, Minsu; Park, Nohpill

doi:10.1109/imtc.2009.5168589

Cited by 7 publications

(7 citation statements)

References 16 publications

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“…Instead of accumulating residues modulo M, reduction can be performed by subtracting multiples of M. Papers that take this approach include [5,[16][17][18][19]. Algorithm 1 is typical.…”

Section: Classes Of Modular Multiplicationmentioning

confidence: 99%

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Revisiting Sum of Residues Modular Multiplication

Kong

Phillips

2010

Journal of Electrical and Computer Engineering

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In the 1980s, when the introduction of public key cryptography spurred interest in modular multiplication, many implementations performed modular multiplication using a sum of residues. As the field matured, sum of residues modular multiplication lost favor to the extent that all recent surveys have either overlooked it or incorporated it within a larger class of reduction algorithms. In this paper, we present a new taxonomy of modular multiplication algorithms. We include sum of residues as one of four classes and argue why it should be considered different to the other, now more common, algorithms. We then apply techniques developed for other algorithms to reinvigorate sum of residues modular multiplication. We compare FPGA implementations of modular multiplication up to 24 bits wide. The sum of residues multipliers demonstrate reduced latency at nearly 50% compared to Montgomery architectures at the cost of nearly doubled circuit area. The new multipliers are useful for systems based on the Residue Number System (RNS).

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“…Instead of accumulating residues modulo M, reduction can be performed by subtracting multiples of M. Papers that take this approach include [5,[16][17][18][19]. Algorithm 1 is typical.…”

Section: Classes Of Modular Multiplicationmentioning

confidence: 99%

“…Note that the carry-save representation is a type of redundant representation that has been applied to other modular multiplication algorithms [15,19,31]. We will keep using this technique to enhance the sum of residues modular multiplier.…”

Section: Reinvigorating Sum Of Residuesmentioning

confidence: 99%

Revisiting Sum of Residues Modular Multiplication

Kong

Phillips

2010

Journal of Electrical and Computer Engineering

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“…Then, the set of partial products are reduced into two final sum and carry vectors using a CSA network. This CSA network is composed of efficient compressors reported in [13] instead of full adders and half adders. At each level of the CSA carry and sum bits are produced and are fed to the next subsequent level.…”

Section: Introductionmentioning

confidence: 99%

Modulo 2ⁿ + 1 squarer design for efficient hardware implementation

Modugu

Kim

et al. 2014

2014 International SoC Design Conference (ISOCC)

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In this work, an efficient hardware architecture of modulo 2 n + 1 squarer is proposed and validated. The proposed modulo 2 n + 1 squarer use novel compressor designs and sparse tree adders as primitive building blocks for fast low-power operations in three major functional modules including partial products generation module, partial products reduction module and final stage addition module. The resulting modulo 2 n + 1 squarer has been implemented in standard CMOS (Complementary Metal-Oxide Semiconductor) cell technology and compared both qualitatively and quantitatively with the existing hardware implementations. The unit gate model analysis and the experimental results show that the proposed implementation is faster and consume less power than existing hardware implementations.

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“…According to Cruiger"s [3], three different multiplication architectures are proposed: The first architecture is designed by using a (n+1) × (n+1) bits multiplier followed by modulo adders to correct errors caused by carry. The second architecture is realized by using modulo 2 n +1 adder, which consists of a carry-save adder and a final carry-select addition unit to reduce design complexity [2]. The third architecture, is realized by modifying the second architecture by reducing the circuit area significantly and by introducing a bit-pair recoding scheme in the carry-save adder block [3] operating speed is increased.…”

Section: Introductionmentioning

confidence: 99%

“…The third architecture, is realized by modifying the second architecture by reducing the circuit area significantly and by introducing a bit-pair recoding scheme in the carry-save adder block [3] operating speed is increased. The last two architectures are suitable for full-custom design [2], because they increase design challenges such as layout and fabrication complexity. Later, Zimmermann [4], implemented a new high speed, low power modulo 2 n +1 multiplier which has a three major parts: partial products generation stage, partial product reduction stage, and the final addition stage.…”

Section: Introductionmentioning

confidence: 99%

Area and Power Efficient Self-Checking Modulo 2^n +1 Multiplier

Mounika¹,

Singh²

2013

IJCA

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Modulo 2 n +1 multiplier is the key block in the circuit implementation of cryptographic algorithm such as IDEA and also widely used in the area of data security applications such as residue arithmetic, digital signal processing, and data encryption that demands low-power, area and high-speed operation. In this paper, a new circuit implementation of an area and power efficient self-checking modulo 2 n +1 multiplier based on residue codes are proposed. Modulo 2 n +1 multiplier has the three major stages: partial product generation stage, partial product reduction stage, and the final adder stage. The last two stages determine the speed and power of the entire circuit. An efficient self-checking modulo 2 n + 1 multiplier based on residue codes are proposed to detect errors online at each single gate during the data transmission and produce an error at the gate output, which may propagate through the subsequent gates and generate an error at the output of the modulo multiplier. The proposed self-checking modulo multipliers for various values of input are specified in Verilog Hardware Description Language (HDL), simulated by using XILINX ISE and synthesized using cadence RTL encounter tool.

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A fast low-power modulo 2<sup>n</sup>+1 multiplier design

Cited by 7 publications

References 16 publications

Revisiting Sum of Residues Modular Multiplication

Revisiting Sum of Residues Modular Multiplication

Modulo 2ⁿ + 1 squarer design for efficient hardware implementation

Area and Power Efficient Self-Checking Modulo 2^n +1 Multiplier

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A fast low-power modulo 2<sup>n</sup>+1 multiplier design

Cited by 7 publications

References 16 publications

Revisiting Sum of Residues Modular Multiplication

Revisiting Sum of Residues Modular Multiplication

Modulo 2n + 1 squarer design for efficient hardware implementation

Area and Power Efficient Self-Checking Modulo 2^n +1 Multiplier

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Modulo 2ⁿ + 1 squarer design for efficient hardware implementation