A fast, predictable FPGA with PLLs, dual port SRAMs and active repeaters

Abstract

To meet the needs of ever demanding customers, today's Field Programmable Gate Arrays (FPGAs) must provide both features and performance. A new FPGA architecture is presented that provides solutions to both of these requirements. Patented active repeater technology provides predictable high-performance (1). Standard features are enhanced by the inclusion of analog PLLs, dual port SRAMs and the ability to interface to multiple VO interface standards.

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

“…[19][20][21][22][23] Besides, fieldprogramable gate arrays (FPGAs) typically require 2-read= write (2RW) DP SRAM for their block memories. [24][25][26][27][28][29] However, the DP SRAM has inherent disturbance issues whenever an access conflict occurs simultaneously from both ports. 1,2) Thus, we have been proposed a highly symmetrical DP SRAM bitcell design without any area overhead.…”

MCSoC: a platform for clock managed systems on a chip

“…The include Phase-Locked Loops (PLL) and/or Delay-Locked Loops (DLL) together with clock dividers and interface circuits. The flexibility and programmability they provide is critical to the scope of applications they can support [12]. These clock managers can perform clock buffering, drive the distribution networks, and simultaneously eliminate clock skew.…”