A fast single chip implementation of 8192 complex points FFT

Bidet, E.; Joanblanq, C.; Senn, P.

doi:10.1109/cicc.1994.379735

Cited by 7 publications

(5 citation statements)

References 9 publications

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“…The legacy fft, shown in figure 5, increases the number of integer bits by 2 for every radix 2 2 stage which is the worst case bit growth possible. 3 The SOPS technique is now applied to this design by modifying the scale factor (or equivalently the number of integer bits) at the different stages, while retaining the same complexity. The block diagram of the new design is shown in 6.…”

Section: A Rotated Fftmentioning

confidence: 99%

“…In fixed point design, the usual technique to optimally scale the outputs at different stages is the Convergent Block Floating Point method (CBFP) [3]. In this method each of the N/r output streams are assigned a scale factor so as to optimally utilise the bit-widths before passing on to the next stage.…”

Section: Traditional Fft Designmentioning

confidence: 99%

“…Even if a separate adder is needed for multiplying the input by -1, it still needs to be done only at the input and not at every stage. 3 The format for the numbers is as follows:"13,1,'tc'" means a twos complement number with 13 total bits and 1 integer bit Rounding was employed in CBFP to compare the proposed designs against the best possible design. The figure shows a significant performance gain of about 16 dB with the R-SOPS FFT compared to the legacy design.…”

Section: A Rotated Fftmentioning

confidence: 99%

“…A lot of work has gone into designing efficient architectures like radix 2, radix 2 2 [1], radix 2 3 [2] and split radix algorithm. Fixed point FFT designs have largely used the complex but optimal Convergent Block Floating Point (CBFP) method [3]or its variants [4]. This method essentially scales the output of every stage appropriately to maximally utilise the dynamic range and hence gets the best Signal to Quantization Noise Ratio(SQNR) for a given number of bits.…”

Section: Introductionmentioning

confidence: 99%

“…In OFDM, the data is sent on orthogonal tones and an IFFT at the transmitter and an FFT at the receiver multiplex and demultiplex the data respectively. Many FFT designs for OFDM systems have also used the CBFP technique as reported in [5], [3].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Exploiting signal and noise statistics for fixed point FFT design optimization in OFDM systems

Ramakrishnan

Balakrishnan

Ramasubramanian

2010

2010 National Conference on Communications (NCC)

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Scaling the different stage outputs in an FFT appropriately is crucial for getting a good Signal to Quantization noise ratio (SQNR) in fixed point FFT design. Traditional designs have either handled this through Convergent block floating point technique (CBFP), which has memory, computation and latency penalties or through time consuming simulations. In this paper, we consider the special case of FFT design for OFDM transceivers. We exploit the Gaussian nature of OFDM signals to predict the bit-growth of the signal through the various stages of the FFT and propose a technique to scale the signal appropriately. Additionally, we investigate the quantization error profile and propose a technique to improve SQNR by exploiting the presence of null tones at the band edges. With the proposed techniques, the performance comes close to the CBFP design, with no increase in complexity compared to existing static designs. Simulation results illustrating the performance improvements of the proposed technique are presented.

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Section: A Rotated Fftmentioning

confidence: 99%

Section: Traditional Fft Designmentioning

confidence: 99%

Section: A Rotated Fftmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Exploiting signal and noise statistics for fixed point FFT design optimization in OFDM systems

Ramakrishnan

Balakrishnan

Ramasubramanian

2010

2010 National Conference on Communications (NCC)

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0.5-μm CMOS circuits for demodulation and decoding of an OFDM-based digital TV signal conforming to the European DVB-T standard

Toso

Combelles

Galbrun

et al. 1998

IEEE J. Solid-State Circuits

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FDF, a 512-TAP FIR filter using a mixed temporal-frequential approach

Bidet

Cardin²,

Kouam³

et al.

Proceedings of the IEEE 1995 Custom Integrated Circuits Conference

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This paper presents a newly developed chip which performs long Finite Impulse Response (FIR) filtering (up to 512 coefficients). By using an innovative architecture based on small Fast Fourier Transforms (FFT) and short FIR filters, one can achieve such a function on a single chip at a reasonable price : FDF (short for Frequency Domain Filter), 1 cm2 in area with 1 million transistors, has been designed in a 3.3V 0 . 5~ triple metal level technology.

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A fast single chip implementation of 8192 complex points FFT

Cited by 7 publications

References 9 publications

Exploiting signal and noise statistics for fixed point FFT design optimization in OFDM systems

Exploiting signal and noise statistics for fixed point FFT design optimization in OFDM systems

0.5-μm CMOS circuits for demodulation and decoding of an OFDM-based digital TV signal conforming to the European DVB-T standard

FDF, a 512-TAP FIR filter using a mixed temporal-frequential approach

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