A fast transistor-chaining algorithm for CMOS cell layout

Hwang, Chi-Yi; Hsieh, Y.-C.; Lin, Youn-Long; Hsu, Yung-Feng

doi:10.1109/43.55207

Cited by 36 publications

(18 citation statements)

References 17 publications

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“…The first task calculates a linear arrangement of the p and n transistors along the diffusion strips [9,10]. The second task find routes to connect transistors using the available metal layers.…”

Section: A Cell Synthesismentioning

confidence: 99%

A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing

Cortadella

Petit

Fernandez

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-An approach for cell routing using gridded design rules is proposed. It is technology-independent and parameterizable for different fabrics and design rules, including support for multiple-patterning lithography. The core contribution is a detailed-routing algorithm based on a Boolean formulation of the problem. The algorithm uses a novel encoding scheme, graph theory to support floating terminals, efficient heuristics to reduce the computational cost and minimization of the number of unconnected pins in case the cell is unroutable. The versatility of the algorithm is demonstrated by routing single-and doubleheight cells. The efficiency is ascertained by synthesizing a library with 127 cells in about one hour and a half of CPU time. The layouts derived by the implemented tool have also been compared with the ones from a commercial library, thus showing the competitiveness of the approach for gridded geometries.

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Section: A Cell Synthesismentioning

confidence: 99%

A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing

Cortadella

Petit

Fernandez

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The fast method discussed in [26] is implemented to perform the chaining. In this method, the cell circuit is represented as a bipartite graph.…”

Section: A Layout Topology Generationmentioning

confidence: 99%

“…• Find maximum compatible set of edges (optimal chaining) using the depth-first search with tree pruning as in [26] 5…”

Section: Variant Of Bipartite Matching W/ Clusteringmentioning

confidence: 99%

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

Ghaida

Gupta

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Design rules have been the primary contract between technology developers and designers and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. The framework essentially creates a virtual standard-cell library and performs the evaluation based on the virtual layouts. Due to the focus on the exploration of rules at an early stage of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). Such a framework can be used to co-evaluate and co-optimize design rules, patterning technologies, layout methodologies, and library architectures.

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“…• Find maximum compatible set of edges (optimal chaining) using the depth-first search with tree pruning as in [24] 5…”

Section: A Layout Topology Generationmentioning

confidence: 99%

A framework for early and systematic evaluation of design rules

Ghaida

Gupta

2009

Proceedings of the 2009 International Conference on Computer-Aided Design

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Abstract-Design rules have been the primary contract between technology and design and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. Due to the focus on co-exploration in early stages of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). The framework is used to efficiently co-evaluate several debatable rules (evaluation for a 104-cell library takes 20 minutes). Results show that: a) diffusionrounding mainly from diffusion power-straps is a dominant source of variability, b) cell-area overhead of fixed gate-pitch implementation compared to 1D-poly implementation is tolerable (5%) given the improvement in variability, and c) 1D-poly restriction, which improves manufacturability and variability, has almost no area overhead compared to 2D-poly. In addition, we explore gate-spacing rules using our evaluation framework. This exploration yields almost identical values as those of a commercial 65nm process, which serves as a validation for our approach.

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A fast transistor-chaining algorithm for CMOS cell layout

Abstract: We propose a fast algorithm for the transistor-chaining problem in CMOS functional cell layout based on Uehara and van Manuscript

Cited by 36 publications

References 17 publications

A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing

A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

A framework for early and systematic evaluation of design rules

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