A faster phase frequency detector using transmission gate–based latch for the reduced response time of the PLL

Koithyar, Aravinda; Ramesh, T. K.

doi:10.1002/cta.2449

Cited by 19 publications

(3 citation statements)

References 14 publications

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“…They go into ‘high’ state only when there is phase lag and phase lead, respectively, at the input. Hence, due to the absence of reset signal, the proposed PLL has near‐zero dead zone, and the PLL is free from blind zone [34].…”

Section: Simulation Results Of the Pllmentioning

confidence: 99%

Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

Koithyar

Ramesh

2020

IET Circuits, Devices & Systems

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In this article, a novel design is presented, for an Integer-N charge pump phase locked loop (PLL). The design is with a resetless phase frequency detector, and with the differential design of charge pump. The voltage-controlled oscillator is of current starved type. The proposed PLL is not having any blind zone and is having near-zero dead zone. When compared to the conventional design, the current mismatch in the charge pump is reduced by 3.21%, and the lock time of the PLL is reduced by 79%. The PLL is intended for 2.4 GHz application, and the obtained lock time is 1.7 μs. The implementation is done with the three-stage ring oscillator, with divider of modulus as 24, in 180 nm TSMC technology. At 1.8 V supply voltage, the circuit consumes 9.72 mW of power.

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Section: Simulation Results Of the Pllmentioning

confidence: 99%

Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

Koithyar

Ramesh

2020

IET Circuits, Devices & Systems

Self Cite

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“…It is particularly difficult to design a frequency synthesizer for mm-wave applications, mainly due to the trade-off among the operating frequency, tuning range and phase noise. [3][4][5] Using high frequency fundamental oscillator in frequency synthesizers is a feasible scheme. However, the phase noise and power consumption are limited by the varactor with low quality factor at mm-wave.…”

Section: Introductionmentioning

confidence: 99%

“…Although the mm‐wave 5G standards provide high capacity and data rates, realizing high performance wideband circuits is difficult in mm‐wave. It is particularly difficult to design a frequency synthesizer for mm‐wave applications, mainly due to the trade‐off among the operating frequency, tuning range and phase noise 3–5 . Using high frequency fundamental oscillator in frequency synthesizers is a feasible scheme.…”

Section: Introductionmentioning

confidence: 99%

A 21.6–30.3 GHz injection‐locked frequency tripler with Darlington injection for 5G communication systems

Qian

et al. 2021

Circuit Theory & Apps

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This paper proposes an injection locked frequency tripler which can cover 27 GHz frequency band of the fifth generation communication. By adopting the Darlington cell as injectors, the injection current is improved greatly and thus obtains a wide locking range. In addition, an inductive peaking technique is proposed to enhance the fundamental rejection and further improve the locking range. Implemented in 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) technology, the post-layout simulation in collaboration with electromagnetic simulation is used to validate the proposed injection locked frequency tripler. The Precess Voltage Temperature (PVT) and Monte Carlo analysis are also performed to check the robustness of the circuit. At 0 dBm injection power, the injection locked frequency triple displays a 33.5% locking range and larger than 27 dB fundamental rejection, while consumes 8.3 mW from 1.2 V supply voltage. The core area is 0.56 × 0.23 mm 2 .

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Low power 10T phase and frequency detector for high frequency phase locked loop

Rajalingam

Srinivasan²,

Jayakumar

et al. 2023

Int J Numerical Modelling

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The high‐frequency circuits used in communication systems significantly depend on the functioning of the Phase‐Locked Loop (PLL). The power consumption is traded with the performance in the high‐frequency PLL. The proposed robust Phase and Frequency Detector (PFD) has multiple benefits of low‐power and reliable functioning at high frequency. The PFD highly contributes to the stable performance of the PLL, and this work proposes a 10T PFD for low‐power. The proposed PFD employs Gate Diffusion Input (GDI) logic based D‐flip flop and the pass transistor logic in the reset path to reduce power consumption. The PFD uses only 10 transistors, enabling a faster reset path and consuming less power at high frequencies. The 10T PFD was designed using 90 nm CMOS PDKs and simulated using CADENCE Specter for functional verification and performance analysis. The 10T PFD achieved a reset time of 61.4 ps at 3 GHz alongside a power consumption of 189.2 nW. Also, the overall power consumption of PLL using the proposed PFD at 3 GHz was demonstrating the effectiveness of 10T PFD over other conventional PFDs.

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A faster phase frequency detector using transmission gate–based latch for the reduced response time of the PLL

Cited by 19 publications

References 14 publications

Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

A 21.6–30.3 GHz injection‐locked frequency tripler with Darlington injection for 5G communication systems

Low power 10T phase and frequency detector for high frequency phase locked loop

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