A fault injection platform for FPGA-based communication systems

Abstract

The resilience of communication systems to soft errors is a major concern in many scenarios, such as when facing stringent dependability constraints or when operating in radiation-harsh environments. Field-Programmable Gate Arrays (FPGAs) are successful platforms for the implementation of communications systems, since they provide the advantages of reconfigurability coupled with a high throughput processing of data streams and lower development costs. When used in radiation-harsh environments, however, FPGAs present a distinct set of challenges that demands specialized evaluation. The large configuration memories of SRAM-based devices are especially susceptible to radiation-induced faults, demanding the evaluation of design's resilience to such phenomena. Therefore, this work

A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

“…The works [33][34][35][36][37][38] present similar platforms for fault injection in CUT (or DUT) and can be used for the same purpose and also make use of the ICAP port for the injection of the faults. However, the works listed focus on evaluating the sensitivity to SEEs of SRAM-based FPGAs, not being focused on CUT.…”

“…The eight configuration frames are divided into two. The first four frames [26][27][28][29] configure the LUTs of slices with Y odd coordinates, while the other four frames [32][33][34][35] configure the slices of the Y coordinate pair. Note that the stack of frames shown in Figure 5 is the same as highlighted in both and Figure 4.…”

An Analysis of Time Domain Reed Solomon Decoder with FPGA Implementation

“…RS decoders for several communication systems have been implemented on FPGA [14], [15]. However because FPGA is vulnerable to soft error, soft error tolerant system design is important for communication systems on FPGA [16].…”

“…Because hardware architecture consisits of simple controller and simple and regular Processing Modules, it is easy to apply fault tolerant techniques such as dual modular redundancy (DMR), or triple modular redundancy (TMR) [19]. Especially, it is good point for the implementation using SRAM-based FPGA, which is vulnerble to soft error occuring during normal operation [16]. Figure 8 depicts the pipelined architecture of the time domain Reed Solomon Decoder applied DMR and TMR.…”