2011
DOI: 10.2197/ipsjtsldm.4.150
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A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures

Abstract: As device feature size decreases, the reliability improvement against soft errors becomes quite necessary. A fault-secure system, in which concurrent error detection is realized, is one of the solutions to this problem. On the other hand, average interconnection delays exceed gate delays which leads to a serious timing closure problem. By using regular-distributed-register architecture (RDR architecture), we can estimate interconnection delays very accurately and their influence can be much reduced even in beh… Show more

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Cited by 11 publications
(5 citation statements)
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“…According to Ref. [7], we set adder cost to be 1, subtracter cost to be 1, multiplier cost to be 2, and comparator cost to be 1. We also set the interconnection delay coefficient to be C d = 1.0 ns.…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…According to Ref. [7], we set adder cost to be 1, subtracter cost to be 1, multiplier cost to be 2, and comparator cost to be 1. We also set the interconnection delay coefficient to be C d = 1.0 ns.…”
Section: Resultsmentioning
confidence: 99%
“…[5], [7] and an interconnection delay D c (i 1 , i 2 ) between the two islands i 1 and i 2 is proportional to the square of their distance and given by…”
Section: Rdr Architecturementioning
confidence: 99%
“…Regular distributed-register (RDR) architectures proposed in Refs. [2], [17] can predict interconnection delays in high-level synthesis accurately by dividing a chip into uniform-sized islands. It arranges functional units, local registers, and a controller inside an island, and multi-cycle interconnect communication during inter-island data transfer can be also realized.…”
Section: Hdr Architecturementioning
confidence: 99%
“…In RDR architectures, a module can be easily added to an island since it abstracts each module inside. Reference [17] realizes fault-secure high-level synthesis using RDR based on adding functional units to an island. On the other hand, RDR architectures have significant area overhead since they divide a chip into uniform-sized islands.…”
Section: Hdr Architecturementioning
confidence: 99%
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