As battery runtime and overheating problems for portable devices become unignorable, energy-aware LSI design is strongly required. Moreover, an interconnection delay should be explicitly considered there because it exceeds a gate delay as the semiconductor devices are downsized. We must take account of energy efficiency and interconnection delays even in high-level synthesis. In this paper, we first propose a huddle-based distributed-register architecture (HDR architecture), an island-based distributed-register architecture for multi-cycle interconnect communications where we can develop several energy-saving techniques. Next, we propose an energy-efficient high-level synthesis algorithm for HDR architectures focusing on multiple supply voltages. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, a huddle, which is composed of functional units, registers, controller, and level converters, are very naturally generated using floorplanning results. By assigning high supply voltage to critical huddles and low supply voltage to non-critical huddles, we can finally have energy-efficient floorplan-aware high-level synthesis. Experimental results show that our algorithm achieves 45% energy-saving compared with the conventional distributed-register architectures and conventional algorithms.

Abstract:In this paper, we propose multiple-supply-voltages aware high-level synthesis algorithm for HDR architectures which realizes high-speed and high-efficient circuits. We propose three new techniques: virtual area estimation, virtual area adaptation, and floorplanning-directed huddling, and integrate them into our HDR architecture synthesis algorithm. Virtual area estimation/adaptation effectively estimates a huddle area by gradually reducing it during iterations, which improves the convergence of our algorithm. Floorplanningdirected huddling determines huddle composition very effectively by performing floorplanning and functional unit assignment inside huddles simultaneously. Experimental results show that our algorithm achieves about 29% run-time-saving compared with the conventional algorithms, and obtains a solution which cannot be obtained by our original algorithm even if a very tight clock constraint is given. Keywords: high-level synthesis, energy-optimization, interconnection delay, multiple supply voltages, distributed-register architecture Classification: Integrated circuits References[1] S. Abe, M. Yanagisawa, and N. Togawa, "An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures,"

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Two new variants of glucose 6-phosphate dehydrogenase (G6PD) deficiency associated with chronic nonspherocytic hemolytic anemia were discovered in Japan. Gd(-) Tokushima was found in a 17-years-old male whose erythrocytes contained 4.4% of normal enzyme activity. Partially purified enzyme revealed a main band of normal electrophoretic mobility with additional two minor bands of different mobility; normal Km G6P, and Km NADP five-to sixfold higher than normal; normal utilization of 2-deoxy-G6P, galactose-6P, and deamino-NADP; marked thermal instability; a normal pH curve; and normal Ki NADPH. The hemolytic anemia was moderate to severe. Gd(-) Tokyo was characterized from a 15-year-old male who had chronic nonspherocytic hemolytic anemia of mild degree. The erythrocytes contained 3% of normal enzyme activity, and partially purified enzyme revealed slow electrophoretic mobility (90% of normal for both a tris-hydrochloride buffer system and a tris-EDTA-borate buffer system, and 70% of normal for a phosphate buffer system); normal Km G6P and Km NADP; normal utilization of 2-deoxy-G6P, galactose-6P, and deamino-NADP; greatly increased thermal instability; a normal pH curve; and normal Ki NADPH. These two variants are clearly different from hitherto described G6PD variants, including the Japanese variants Gd(-) Heian and Gd(-) Kyoto. The mothers of both Gd(-) Tokushima and Gd(-) Tokoyo were found to be heterozygote by an ascorbate-cyanide test.

This paper describes a compact transmitting bandpass filter using dielectric resonators for PCS microcellular base station. We propose n.ew size reduced capacitive loaded TM dual mode reaouators that consist of monoblock high K ceramics. The electrical performance of the filter constructed by these resonators is designed by using Idud mode dielectric transmission line method. A! :six pole bandpass filter at 1.9GHz band is manufactured. It has center frequency of 1.87GHz, low insertion loss of l.ldB and small dimensions of 20~20x60 mm.