MH⁴ : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures

Abstract

Abstract:In this paper, we propose multiple-supply-voltages aware high-level synthesis algorithm for HDR architectures which realizes high-speed and high-efficient circuits. We propose three new techniques: virtual area estimation, virtual area adaptation, and floorplanning-directed huddling, and integrate them into our HDR architecture synthesis algorithm. Virtual area estimation/adaptation effectively estimates a huddle area by gradually reducing it during iterations, which improves the convergence of our algorithm. Floorplanningdirected huddling determines huddle composition very effectively by performing floorplanning and functional unit assignment inside huddles simultaneously. Experimental results show that our algorithm achieves about 29% run-time-saving compared with the conventional algorithms, and obtains a solution which cannot be obtained by our original algorithm even if a very tight clock constraint is given. Keywords: high-level synthesis, energy-optimization, interconnection delay, multiple supply voltages, distributed-register architecture Classification: Integrated circuits References[1] S. Abe, M. Yanagisawa, and N. Togawa, "An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures,"

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

“…We have compared our proposed SAAV algorithm (AVHDR in Table I) to a traditional shared-register architecture synthesis algorithm [8], a GDR architecture synthesis algorithm [9], MCAS for RDR architectures [4], an HDR architecture synthesis algorithm with single supply voltage [1], an HDR architecture synthesis algorithm with multiple supply voltages [1](MHDR [1] in Table I). We further compared our algorithm with the following strategy: we first performed the existing dynamic multiple-supply-voltages-aware voltage assignment to each operation [3]; Based on this voltage assignment, we performed [1] for AVHDR architectures ( [3]+ [1] in Table I).…”

“…We further compared our algorithm with the following strategy: we first performed the existing dynamic multiple-supply-voltages-aware voltage assignment to each operation [3]; Based on this voltage assignment, we performed [1] for AVHDR architectures ( [3]+ [1] in Table I). Table I summarizes the experimental results.…”

“…The experimental results show that all energy consumption of AVHDR is reduced by a maximum of 79.8% and an average of 52.9% compared with the other algorithms. Since the energy consumption [3]+ [1] is reduced compared with the other algorithms without dynamic multiple supply voltages, dynamic multiple supply voltages can reduce energy consumption effectively. The energy consumption of AVHDR is reduced by a maximum of 47.7% and an average of 39.0% compared with [3]+ [1].…”

“…In the virtual area adaptation step, we gradually decrease the virtual area overhead as the iterations proceed. The same algorithms as HDR architecture [1] can be applied to these algorithms.…”

“…In multi-cycle interconnect communication, the data is first stored in a local register and then transferred between local registers. Several distributed-register architectures family, GDR [9], RDR [4], HDR [1], [2], and synthesis algorithms targeting them have been proposed, but dynamic multiple supply voltages cannot be applied for these architectures at all.…”