A fault tolerant parallel-prefix adder for VLSI and FPGA design

Martinez, Chris D.; Bollepalli, L. P. Deepthi; Hoe, David H. K.

doi:10.1109/ssst.2012.6195145

Cited by 11 publications

(9 citation statements)

References 4 publications

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“…As such, the methods discussed in this paper illustrate techniques for implementing fault tolerance on a critical component that could be applied to other systems on an FPGA. This paper expands upon our work previously reported in conference papers regarding the characterization of arithmetic logic on FPGAs [2] and the implementation of fault tolerant adder designs on FPGAs [3]. In particular, this paper examines the implementation of fault tolerance in adders that utilize a parallel-prefix scheme for rapid computation of the carry signals.…”

Section: Introductionmentioning

confidence: 69%

“…With the sparse Kogge-Stone designs, only the RCA chains are monitored for faults and several clock cycles may be needed to recover from a fault. Additional tradeoffs in terms of time and area are necessary to make the sparse carry trees also fault tolerant [3].…”

Section: Resultsmentioning

confidence: 99%

“…By comparing the two sets of carries when they are all available, a scheme can be developed for isolating a potential fault to one of the regions labeled (1), (2), or (3) as in Figure 12. For further details on this scheme, the interested reader is referred to our discussion in [3].…”

Section: Fault-tolerant Adder Designsmentioning

confidence: 99%

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FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

2013

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This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular redundancy, roving, and gradual degradation. A parallel-prefix adder based upon the Kogge-Stone configuration is compared with the simple ripple carry adder (RCA) design. The Kogge-Stone design utilizes a sparse carry tree complemented by several smaller RCAs. Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving and gradual degradation. A triple modular redundant ripple carry adder (TMR-RCA) is used as a point of reference. Simulation and experimental measurements on a Xilinx Spartan 3E FPGA platform are carried out. The TMR-RCA is found to have the best delay performance and most efficient resource utilization for an FPGA fault-tolerant implementation due to the simplicity of the approach and the use of the fast-carry chain. However, the superior performance of the carry-tree adder over an RCA in a VLSI implementation makes this proposed approach attractive for ASIC designs.

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Section: Introductionmentioning

confidence: 69%

Section: Resultsmentioning

confidence: 99%

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FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

2013

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“…The design proposed in [1] can detect and correct error only if any one of the RCA becomes faulty as the clock signal to the bit counter is stopped if the fault is found in any of the RCA. In order to correct the errors in more than one RCA a 16-bit register is added to the design which holds the sum output from the comparator.…”

Section: Fig7: Timing Diagram For Lower Half Sks Addermentioning

confidence: 99%

“…The improvement introduced in the proposed design is the reduction in the error recovery time which is very critical in any fault tolerant circuit. As the corrected sum output is available in the register after all the RCA are tested the final sum output can be sampled from the register and no extra clock cycles are required to correct error after fault detection as required in the design proposed in [1].…”

Section: Fig7: Timing Diagram For Lower Half Sks Addermentioning

confidence: 99%

Improved Fault Tolerant Sparse KOGGE Stone ADDER

Kondalkar¹,

Chavan²,

Narashimaraja³

2013

IJCA

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A fault tolerant adder implemented using Kogge-stone configuration can correct the error due to inherent redundancy in the carry tree but no error detection is possible. This proposed design is based on fault tolerant adder [1] that uses Sparse kogge-stone adder that is capable of both fault detection and correction. Fault tolerance is achieved by using two additional ripple carry adders that form the basis of triple mode redundancy adder. Triple mode redundancy is one of the most common methods used to create fault tolerant designs in both ASIC and FPGA implementations. The latency will be increased because of the voter in the circuit's critical path. More advanced fault tolerant methods exist including roving and graceful degradation approaches. Allowing fault tolerance to operate at different levels of abstraction might facilitate a more cost-effective design. Several enhancements are introduced in the design; the error recovery time is reduced by using a 16-bit register, error correction due to fault in multiple ripple carry adders is included which improves the reliability of the circuit. The power analysis and the timing analysis for the estimation of setup time and hold time is also performed. General TermsSparse Kogge-Stone adder, Triple Mode Redundancy, Fault tolerant.

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Real-time fault tolerant full adder design for critical applications

Kumar

Sharma

2016

Engineering Science and Technology, an International Journal

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a b s t r a c tIn the complex computing system, processing units are dealing with devices of smaller size, which are sensitive to the transient faults. A transient fault occurs in a circuit caused by the electromagnetic noises, cosmic rays, crosstalk and power supply noise. It is very difficult to detect these faults during offline testing. Hence an area efficient fault tolerant full adder for testing and repairing of transient and permanent faults occurred in single and multi-net is proposed. Additionally, the proposed architecture can also detect and repair permanent faults. This design incurs much lower hardware overheads relative to the traditional hardware architecture. In addition to this, proposed design also provides higher error detection and correction efficiency when compared to the existing designs. Ó 2016 The Authors. Publishing services by Elsevier on behalf of Karabuk University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

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A fault tolerant parallel-prefix adder for VLSI and FPGA design

Cited by 11 publications

References 4 publications

FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

Improved Fault Tolerant Sparse KOGGE Stone ADDER

Real-time fault tolerant full adder design for critical applications

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