Real-time fault tolerant full adder design for critical applications

Kumar, Pawan; Sharma, R. K.

doi:10.1016/j.jestch.2016.05.001

Cited by 21 publications

(9 citation statements)

References 28 publications

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“…The Self Repairing Adder design approach [31] fails while multiple wrong inputs are provided to the adder and are unable to identify the location. In Real-Time Fault-Tolerant Full Adder design approach the number of hardware components is high due to redundancy in design and thus are more costly [32]- [33]. Due to the redundant circuit design, critical path delay is increased and thereby increases the overall circuit delay [34]- [38].…”

Section: Existing Fault-tolerant Circuit Designs Approachmentioning

confidence: 99%

A Full Adder Design with CNFETs for Real Time, Fault Tolerant and Mission Critical Applications

Srinivasulu¹,

Saini²,

Kumawat³

2020

ELS

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The VLSI based circuits often pose challenges in the form of various faults (such as transient faults, permanent faults, stuck-at-faults). These faults appear even after testing also. They occur because of reduction in the size of the circuit or during realtime implementation, as these faults are difficult to detect. It is very important to detect and rectify all such faults to make the system foolproof and achieve expected functionality. In this paper, 12 transistors based, full adder circuit (12T-FAC) using Carbon Nanotube Field Effect Transistor (CNFET) technology is proposed. The proposed design based on CNFET provides high fault resistance towards transient, permanent faults and works with least power, delay and power-delay product (PDP). Later, features like fault detection and correction circuit have been added in 12T-FAC. The final version of full adder circuit capable of correcting errors has been used in designing applications like multipliers. The proposed full adder circuit was designed with CNFET technology, simulated at 32 nm with supply voltage +0.9 V using the Cadence Virtuoso CAD tool. The model used is Stanford PTM.

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Section: Existing Fault-tolerant Circuit Designs Approachmentioning

confidence: 99%

A Full Adder Design with CNFETs for Real Time, Fault Tolerant and Mission Critical Applications

Srinivasulu¹,

Saini²,

Kumawat³

2020

ELS

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“…The author in [11] proposed a self checking adder which can detect the faults. There is another proposed fault tolerant adder having different functional unit F1 as shown in Fig.5.…”

Section: B Dft (Design For Testability) For Double Fault 1) Full Addermentioning

confidence: 99%

“…The design can repair single and the double faults. The author in [11] designed a self repairing circuit to repair the faults in adder. In fig.7 there is tolerant circuit in which value of Sum/diff output bit is selected by the multiplexer under the control of …”

Section: Fault Tolerant Full Adder and Full Subtractormentioning

confidence: 99%

Design of Fault Tolerant Full Adder and Full Subtractor

Mahajan¹

2018

IJRASET

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Now days, the complexity of integrated circuits is increasing while reliability of the components is decreasing due to small gates and transistor. One of the impacts of technology scaling is more sensitivity to transient and permanent faults. So, fault tolerant system plays important role in critical application where immediate human action is not possible. For reliable and efficient operation of a system, the detection of the transient fault is necessary. It is very difficult to detect these faults offline. The fault tolerant circuits can detect the faults and tolerate the detected faults. There are many fault tolerant full adder and full subtractor which can detect these faults online. So, an efficient fault tolerant design is proposed for full adder and full subtractor in this paper which can detect the faults with their exact location and also tolerate the faults. The proposed designs can detect the faults in single and multi net. The design has less area overhead and has less power requirements as compared to the previous techniques.

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“…Arithmetic processing units are basic building blocks of many digital systems like Microprocessors, Digital signal processors, and most of the dedicated signal processing circuits [1][2][3][4][5][6]. For any arithmetic processing unit, adders are one of the most crucial components because of its resource consumption and the delay involved in processing.…”

Section: Introductionmentioning

confidence: 99%

“…Adders also form a part of multipliers which is another resource intensive component of arithmetic circuits [7]. For an efficient implementation of arithmetic circuits, the choice of a particular adder thus becomes an important design consideration [1][2][3][4][5][6][7][8][9]. Considering the importance associated with the implementation of an adder, in this work, some of the existing adder implementations are compared with respect to the delay incurred, resource utilization and power consumption.…”

Section: Introductionmentioning

confidence: 99%