Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017 2017
DOI: 10.23919/date.2017.7927200
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A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration

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Cited by 10 publications
(6 citation statements)
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“…This introduces the possibility that a defender strategy could be simply to increase the cost required by the adversary to play their favorite strategy. In fact, this is exactly what one class of HTH countermeasure does, often via obfuscating the circuit, as in [58][59][60][61][62][63][64][65][66][67]. As with other refinements of our game, were we to include such strategies, we may want to reconsider utility functions; this is explored in detail in Sect.…”
Section: Exploring the Results With Gamerunnermentioning
confidence: 99%
“…This introduces the possibility that a defender strategy could be simply to increase the cost required by the adversary to play their favorite strategy. In fact, this is exactly what one class of HTH countermeasure does, often via obfuscating the circuit, as in [58][59][60][61][62][63][64][65][66][67]. As with other refinements of our game, were we to include such strategies, we may want to reconsider utility functions; this is explored in detail in Sect.…”
Section: Exploring the Results With Gamerunnermentioning
confidence: 99%
“…Tian et al [61] reported better area utilization figures with a fine-grained implementation of functions onto a programmable transistor array. FPTAs employ configurable array of transistors which are regularly-arranged into rows and columns.…”
Section: Field Programmable Transistor Array (Fpta)mentioning
confidence: 99%
“…Transistor-array based: The Field Programmable Transistor Array (FPTA) proposed by Tian et al [61] is shown to have a 15% lower area utilization compared to the baseline architecture of Altera Stratix EP1S10, as shown in TABLE 1.…”
Section: Lut-based: Figurementioning
confidence: 99%
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“…The key issue is then how to find an ideal portion of a design, given as behavioral decription for high-level synthesis (HLS), to map onto an eFPGA [15] to enable effective design obfuscation.…”
Section: Embedded Fpgamentioning
confidence: 99%