A fill-unit approach to multiple instruction issue

Many contemporary multiple issue processors employ out-of-order scheduling hardware in the processor pipeline. Such s c heduling hardware can yield good performance without relying on compile-time scheduling. The hardware can also schedule around unexpected run-time occurrences such a s c a c he misses. As issue widths increase, however, the complexity o f s u c h s c heduling hardware increases considerably and can have an impact on the cycle time of the processor. This paper presents the design of a multiple issue processor that uses an alternative approach called miss path scheduling or MPS. S c heduling hardware is removed from the processor pipeline altogether and placed on the path between the instruction cache and the next level of memory. Scheduling is performed at cache miss time, as instructions are received from memory. Scheduled blocks of instructions are issued to an aggressively clocked in-order execution core. Details of a hardware scheduler that can perform speculation are outlined and shown to be feasible. Performance results from simulations are presented that highlight the e ectiveness of an MPS design.

MPS: miss-path scheduling for multiple-issue processors

Banerjia

Sathaye

Menezes

et al. 1998

A trace cache microarchitecture and evaluation

Rotenberg

Bennett

Smith

1999

AbstractÐAs the instruction issue width of superscalar processors increases, instruction fetch bandwidth requirements will also increase. It will eventually become necessary to fetch multiple basic blocks per clock cycle. Conventional instruction caches hinder this effort because long instruction sequences are not always in contiguous cache locations. Trace caches overcome this limitation by caching traces of the dynamic instruction stream, so instructions that are otherwise noncontiguous appear contiguous. In this paper, we present and evaluate a microarchitecture incorporating a trace cache. The microarchitecture provides high instruction fetch bandwidth with low latency by explicitly sequencing through the program at the higher level of traces, both in terms of 1) control flow prediction and 2) instruction supply. For the SPEC95 integer benchmarks, trace-level sequencing improves performance from 15 percent to 35 percent over an otherwise equally sophisticated, but contiguous, multiple-block fetch mechanism. Most of this performance improvement is due to the trace cache. However, for one benchmark whose performance is limited by branch mispredictions, the performance gain is almost entirely due to improved prediction accuracy.

Properties of rescheduling size invariance for dynamic rescheduling-based VLIW cross-generation compatibility

Conte

Sathaye

2000

The object-code compatibility problem in VLIW architectures stems from their statically scheduled nature. Dynamic rescheduling DR 1 is a technique to solve the compatibility problem in VLIWs. DR reschedules program code pages at rst-time page faults i.e., when the code pages are accessed for the rst time during execution. Treating a page of code as the unit of rescheduling makes it susceptible to hazard of changes in the page-size during the process of rescheduling. This paper proves that the changes in the page-size are only due to insertion and or deletion of NOPs in the code. Further, it presents an ISA encoding called list encoding, which does not require explicit encoding of the NOPs in the code. A property o f t h e encoding called rescheduling-size invariance RSI is presented and it is proved that the list encoding satis es this property.