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Recent supers calar processorsissue four tnstructzons per cycle.

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The IA-64 architecture is rich with features that enable aggressive exploitation of instruction-level parallelism. Features such as speculation, predication, multiway branches and others provide compilers with new opportunities for the extraction of parallelism in programs. Code scheduling is a central component in any compiler for the IA-64 architecture. This paper describes the implementation of the global code scheduler GCS in Intel's compiler for the IA-64 architecture. GCS schedules code over acyclic regions of control ow. There is a tight coupling between the formation and scheduling of regions. GCS employs a new path based data dependence representation that combines control ow a n d data dependence information to make data analysis easy and accurate. This paper provides details of this representation. The scheduler uses a novel instruction scheduling technique called Wavefront s c heduling. The concepts of wavefront s c heduling and deferred compensation are explained to demonstrate the e cient generation of compensation code while scheduling. This paper also presents P-ready code motion, an opportunistic instruction level tail duplication which aims to strike a b a l a n c e b e t ween code expansion and performance potential. Performance results show greater than 30 improvement in speedup for wavefront s c heduling over basic block s c heduling on the Itanium microarchitecture.