Wavefront scheduling: path based data representation and scheduling of subgraphs

Bharadwaj, Jay; Menezes, Kishore N.; McKinsey, Chris

doi:10.1109/micro.1999.809464

Cited by 16 publications

(21 citation statements)

References 12 publications

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“…The schedulers described in this report use the superblock [27] [28] and hyperblock [29,30] as the global scheduling region. Wavefront scheduling uses a region consisting of a tree of basic blocks [31].…”

Section: Related Workmentioning

confidence: 99%

Efficient backtracking instruction schedulers

Abraham

Meleis

Baev

Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622)

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Current schedulers for acyclic regions schedule operations in dependence order and never revisit or undo a scheduling decision on any operation. In contrast, backtracking schedulers may unschedule already scheduled operations, in order to make space for the operation currently being scheduled. Backtracking schedulers have the potential for generating better schedules, e.g. more effectively filling branch delay slots, but are more compile-time intensive and therefore, not considered practical for production use.In this report, we first describe conventional cycle and list schedulers followed by two novel backtracking schedulers. The full-backtracking OperBT scheduler enables backtracking for all operations and unschedules already scheduled operations to make space for the current operation, if, among other situations, there is no available slot that satisfies dependence constraints. This scheduler is effective in generating high quality schedules that for instance, successfully fill branch delay slots but likely backtracks too often. The selective backtracking ListBT scheduler enables backtracking only when scheduling certain types of operations, for which backtracking is likely to be advantageous, e.g. branches. When not scheduling these operations (or operations that were displaced through backtracking), the scheduler reverts to efficient scheduling in dependence order. The ListBT scheduler backtracks less often than the OperBT scheduler. Both schedulers successfully fill a large fraction of the branch delay slots and improve performance of the scheduled code significantly.

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Section: Related Workmentioning

confidence: 99%

Efficient backtracking instruction schedulers

Abraham

Meleis

Baev

Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622)

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“…This is because back edges cannot be handled by if-conversion. Note that for each leaf region, we have inserted the interface blocks [4] (depicted in dashes), one for each of its region exits. As a result, the successors of every original node in a leaf region must all reside in that region.…”

Section: Regionsmentioning

confidence: 99%

“…This leads to Figure 1(b), where the blocks 2 -5 have been merged into a new hyperblock HB. In addition, we have inserted the so-called interface blocks [4], I 1 -I 4 at all region exits to simplify the design and implementation of our algorithm. Let us explain briefly the effectiveness of our algorithm using the SEME region R 2 depicted in Figure 1(b).…”

Section: Introductionmentioning

confidence: 99%

Region-Based Partial Dead Code Elimination on Predicated Code

Cai

Gao

Xue

2004

Lecture Notes in Computer Science

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Abstract. This paper presents the design, implementation and experimental evaluation of a practical region-based partial dead code elimination (PDE) algorithm on predicated code in an existing compiler framework. Our algorithm processes PDE candidates using a worklist and reasons about their partial deadness using predicate partition graphs. It operates uniformly on hyperblocks and regions comprising basic blocks and hyperblocks. The result of applying our algorithm to an SEME region is optimal: partially dead code cannot be removed without changing the branching structure of the program or potentially introducing new predicate defining instructions. We present statistic evidence about the PDE opportunities in the 12 SPECint2000 benchmarks. In addition to exhibit small compilation overheads, our algorithm achieves moderate performance improvements in 8 out of the 12 benchmarks on an Itanium machine. Our performance results and statistics show the usefulness of our algorithm as a pass applied before instruction scheduling.

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“…A detailed study of the overall benefits of pointer analysis and its eventual impact on program performance. 3. A comprehensive analysis of the effectiveness of various disambiguation techniques, providing insight into which techniques are most often used.…”

Section: The Memory Disambiguation Framework Implemented In the Intelmentioning

confidence: 99%

On the importance of points-to analysis and other memory disambiguation methods for C programs

2001

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In this paper, we evaluate the benefits achievable from pointer analysis and other memory disambiguation techniques for C/C++ programs, using the framework of the production compiler for the Intel® Itanium™ processor. Most of the prior work on memory disambiguation has primarily focused on pointer analysis, and either presents only static estimates of the accuracy of the analysis (such as average points-to set size), or provides performance data in the context of certain individual optimizations. In contrast, our study is based on a complete memory disambiguation framework that uses a whole set of techniques including pointer analysis. Further, it presents how various compiler analyses and optimizations interact with the memory disambiguator, evaluates how much they benefit from disambiguation, and measures the eventual impact on the performance of the program. The paper also analyzes the types of disambiguation queries that are typically received by the disambiguator, which disambiguation techniques prove most effective in resolving them, and what type of queries prove difficult to be resolved. The study is based on empirical data collected for the SPEC CINT2000 C/C++ programs, running on the Itanium processor.

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Wavefront scheduling: path based data representation and scheduling of subgraphs

Cited by 16 publications

References 12 publications

Efficient backtracking instruction schedulers

Efficient backtracking instruction schedulers

Region-Based Partial Dead Code Elimination on Predicated Code

On the importance of points-to analysis and other memory disambiguation methods for C programs

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