A Fine-Grain Variation-Aware Dynamic &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;${\rm Vdd}$&lt;/tex&gt;&lt;/formula&gt;-Hopping AVFS Architecture on a 32 nm GALS MPSoC

Miro-Panades, Ivan; Beigné, Edith; Thonnart, Yvain; Alacoque, Laurent; Vivet, Pascal; Lesecq, Suzanne; Puschini, Diego; Molnos, Anca; Thabet, Farhat; Tain, Benoit; Chehida, Karim Ben; Engels, Sylvain; Wilson, Robin; Fuin, Didier

doi:10.1109/jssc.2014.2317137

Cited by 22 publications

(8 citation statements)

References 23 publications

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“…To enable fine grained frequency tuning, a Frequency-Locked Loop [52] and two clock dividers (one for the cluster and one for peripherals) are included in the SoC.…”

Section: B Pulp Acceleratormentioning

confidence: 99%

Accelerated Visual Context Classification on a Low-Power Smartwatch

Conti

Palossi

Andri

et al. 2016

IEEE Trans. Human-Mach. Syst.

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Data produced by wearable sensors is key in contexts such as performance enhancement and training help for sports and fitness, continuous monitoring for aging people and for chronic disease management, and in gaming and entertainment. Unfortunately, wearable devices currently on the market are either incapable of complex functionality or severely impaired by short battery lifetime. In this work, we present a smartwatch platform based on an ultra-low power (ULP) heterogeneous system composed by a TI MSP430 microcontroller, the PULP programmable parallel accelerator and a set of ULP sensors, including a camera. The embedded PULP accelerator enables state-of-the-art context classification based on Convolutional Neural Networks (CNNs) to be applied within a sub-10mW system power envelope. Our methodology enables to reach high accuracy in context classification over 5 classes (up to 84%, with 3 classes over 5 reaching more than 90% accuracy), while consuming 2.2mJ per classification, or an ultra-low energy consumption of less than 91uJ per classification with an accuracy of 64%-3.2× better than chance. Our results suggest that the proposed heterogeneous platform can provide up to 500× speedup with respect to the MSP430 within a similar power envelope, which would enable complex computer vision algorithms to be executed in highly power-constrained scenarios.

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“…To enable fine grained frequency tuning, a Frequency-Locked Loop [52] and two clock dividers (one for the cluster and one for peripherals) are included in the SoC.…”

Section: B Pulp Acceleratormentioning

confidence: 99%

Accelerated Visual Context Classification on a Low-Power Smartwatch

Conti

Palossi

Andri

et al. 2016

IEEE Trans. Human-Mach. Syst.

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“…The CGU, highlighted in red in Fig. 4, produces a fast clock from a reference clock by using a flexible configurable frequency lock loop (FLL) [16]. The CGU has its own supply V CGU such that its energy consumption does not affect the decoder measurements.…”

Section: Clock-generation and Test-controller Unitsmentioning

confidence: 99%

“…The authors would like to thank Christian Senning and Lorenz Schmid (formerly EPFL) for their support, Ivan Miro-Padanes (CEA-LETI) for providing the FLL [16] along with support for it, and Marc-André Carbonneau (ÉTS) for the test PCB design. Furthermore, they would like to thank STMicroelectronics for chip fabrication.…”

Section: Acknowledgementmentioning

confidence: 99%

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes

Giard

Balatsoukas‐Stimming

Müller

et al. 2017

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Abstract-Polar codes are a recently proposed class of block codes that provably achieve the capacity of various communication channels. They received a lot of attention as they can do so with low-complexity encoding and decoding algorithms, and they have an explicit construction. Their recent inclusion in a 5G communication standard will only spur more research. However, only a couple of ASICs featuring decoders for polar codes were fabricated, and none of them implements a list-based decoding algorithm. In this paper, we present ASIC measurement results for a fabricated 28 nm CMOS chip that implements two different decoders: the first decoder is tailored toward error-correction performance and flexibility. It supports any code rate as well as three different decoding algorithms: successive cancellation (SC), SC flip and SC list (SCL). The flexible decoder can also decode both non-systematic and systematic polar codes. The second decoder targets speed and energy efficiency. We present measurement results for the first silicon-proven SCL decoder, where its coded throughput is shown to be of 306.8 Mbps with a latency of 3.34 us and an energy per bit of 418.3 pJ/bit at a clock frequency of 721 MHz for a supply of 1.3 V. The energy per bit drops down to 178.1 pJ/bit with a more modest clock frequency of 308 MHz, lower throughput of 130.9 Mbps and a reduced supply voltage of 0.9 V. For the other two operating modes, the energy per bit is shown to be of approximately 95 pJ/bit. The less flexible high-throughput unrolled decoder can achieve a coded throughput of 9.2 Gbps and a latency of 628 ns for a measured energy per bit of 1.15 pJ/bit at 451 MHz.

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“…Digital FLLs [16] are used in many circuits to generate a stable clock, and are also used in dynamic voltage and frequency scaling (DVFS) and adaptive voltage and frequency scaling (AVFS) digital architectures for power management. FLL's main advantages are a fast frequency reconfiguration and a very low area.…”

Section: Frequency-locked-loop and Network's Performance Characterisamentioning

confidence: 99%

“…Indeed, quasi-delay-insensitive (QDI) asynchronous logic is always functional and insensitive to delay variations due to voltage domains, temperature, or process changing. To test our network, four digital frequency locked loops (FLLs) [16] are embedded in a realistic test case. The network is implemented in a 28 nm Fully Depleted Silicon On Insulator (FDSOI) technology at 0.6 V. The obtained energy per bit is of 0.07 pJ/bit per stage, and the latency is 1.1 ns/bit.…”

Section: Introductionmentioning

confidence: 99%

Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits

Chairat¹,

Beigné²,

Miro-Panades³

et al. 2017

JLPEA

Self Cite

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This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT) system. By using a separate communication network, we can address both digital and analog blocks at a lower configuration cost, increasing the overall system power efficiency. As reconfiguration only occurs according to specific events and has to be automatically in stand-by most of the time, our design is fully asynchronous using handshake protocols. The paper presents the circuit's architecture, performance results, and an example of the reconfiguration of frequency locked loops (FLL) to validate our work. We obtain an overall energy per bit of 0.07 pJ/bit for one stage, in a 28 nm Fully Depleted Silicon On Insulator (FDSOI) technology at 0.6 V and a 1.1 ns/bit latency per stage.

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A Fine-Grain Variation-Aware Dynamic <formula formulatype="inline"><tex Notation="TeX">${\rm Vdd}$</tex></formula>-Hopping AVFS Architecture on a 32 nm GALS MPSoC

Cited by 22 publications

References 23 publications

Accelerated Visual Context Classification on a Low-Power Smartwatch

Accelerated Visual Context Classification on a Low-Power Smartwatch

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes

Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits

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