A Finite-Oxide Thickness-Based Analytical Model for Negative Bias Temperature Instability

Kumar, Sanjay; Kim, C.H.; Sapatnekar, Sachin S.

doi:10.1109/tdmr.2009.2028578

Cited by 30 publications

(11 citation statements)

References 43 publications

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“…Accordingly, the Î Ø degradation for a PMOS transistor under DC stress increases asymptotically with time, Ø, as ¡Î Ø ´Øµ » Ø ½ [12]- [15]. We also use a PBTI model where the degradation mechanism is similar to NBTI, but the magnitude of Î Ø degradation is lower.…”

Section: A Impact Of Bti On Delay and Leakagementioning

confidence: 99%

“…If the leakage power of the circuit exceeds its budget value, the nominal value of the leakage power is updated, and this new value is used in (5) for È lkg´Ø ¼µ, as shown in line 17, and adaptive compensation is now repeated on this modified circuit. The process of adaptive compensation (lines 3-9) and technology-mapping for a tighter target delay (lines [13][14][15][16] is performed in an iterative manner, until the circuit delays converge, and the timing specifications are met at all times. In practice, only a few iterations are necessary before the delay converges, as seen from our experiments.…”

Section: : End Ifmentioning

confidence: 99%

“…At this point, ´Ø ·½ µ spec . 15: end for 16: Return the´Ú Ò Ú Ô Î µ tuples at all times Ø ¼ Ø Ò ½ .…”

mentioning

confidence: 99%

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Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits

Kumar

Kim

Sapatnekar

2011

IEEE Trans. VLSI Syst.

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Abstract-Negative bias temperature instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent introduction of Hf-based high-k dielectrics for gate leakage reduction, positive bias temperature instability (PBTI), the dual effect in NMOS transistors, has also reached significant levels. Consequently, designs are required to build in substantial guardbands in order to guarantee reliable operation over the lifetime of a chip, and these involve large area and power overheads. In this paper, we begin by proposing the use of adaptive body bias (ABB) and adaptive supply voltage (ASV) to maintain optimal performance of an aged circuit, and demonstrate its advantages over a guardbanding technique such as synthesis. We then present a hybrid approach, utilizing the merits of both ABB and synthesis, to ensure that the resultant circuit meets the performance constraints over its lifetime, and has a minimal area and power overhead, as compared with a nominally designed circuit.

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Section: A Impact Of Bti On Delay and Leakagementioning

confidence: 99%

Section: : End Ifmentioning

confidence: 99%

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Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits

Kumar

Kim

Sapatnekar

2011

IEEE Trans. VLSI Syst.

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“…There are two widely-used theories for BTI. The reaction-diffusion (R-D) model [1,2] explains the degradation due to the accumulation of positive charges as Si-H bonds at the interface are broken and hydrogen diffuses away; the removal of this stress allows partial restoration of these bonds. The charge-trapping (CT) model [3] provides an alternative explanation, where defects in gate dielectrics can capture charged carriers, causing the threshold voltage to degrade.…”

Section: Circuit-level Analysis Of Agingmentioning

confidence: 99%

What happens when circuits grow old: Aging issues in CMOS design

Sapatnekar¹

2013

2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)

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As CMOS technologies have shrunk to tens of nanometers, aging problems have emerged as a major challenge. There has been tremendous progress in developing new methods for modeling and diagnosing reliability at the level of individual transistors, but much less work on propagating these models to higher levels of abstraction to analyze and optimize the reliability of larger circuits. This talk will provide an introduction to various circuit aging mechanisms and will then discuss research that develops computer-aided design techniques for estimating and enhancing the reliability of large digital circuits, examining solutions that could practically be applied to analyze or improve the lifetime of a design while maintaining consistency to accurate device-level models and the associated physics.CIRCUIT-LEVEL ANALYSIS OF AGING Aging effects are described by the classical bathtub curve: after a steep initial failure rate, the failures level off for a while before rising again, resulting in a bathtub-like shape for the number of failures as a function of time. Aging is strongly sensitivity to process parameter variations, as well as to onchip temperature and supply voltage level changes. Here, we overview analysis methods for prominent aging mechanisms, based on both conventional and newer physical models. Bias temperature instability (BTI) is a device aging phenomenon that causes threshold voltage shifts over long periods of time in the presence of voltage stress at the gate, eventually causing the circuit to fail to meet its specifications. A PMOS transistor in an inverter experiences negative BTI stress when its gate node is at logic 0, and the resulting increase in the threshold voltage is partially reversed when the voltage stress is removed (i.e., a logic 1 is applied). A similar phenomenon of positive BTI affects the threshold voltage of NMOS devices when they are stressed, and relaxes the degradation on the removal of stress. The magnitude of degradation depends on the ratio of the stressed time to unstressed time, i.e., the signal probability (SP) of the gate input. There are two widely-used theories for BTI. The reaction-diffusion (R-D) model [1,2] explains the degradation due to the accumulation of positive charges as Si-H bonds at the interface are broken and hydrogen diffuses away; the removal of this stress allows partial restoration of these bonds. The charge-trapping (CT) model [3] provides an alternative explanation, where defects in gate dielectrics can capture charged carriers, causing the threshold voltage to degrade. Neither theory fully explains experimental observations, and it has been posited that R-D and CT mechanisms coexist. The CT model predicts high variability in small devices, making variability a major factor for memories. For logic circuits, however, large transistors and averaging effects on critical paths significantly mitigate variability [4]. Hot carrier injection (HCI) in MOSFETs is caused by the acceleration of carriers (electrons/holes) under lateral electric fields in th...

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“…We use R-D theory to model the interface defect dynamics, because it appears to consistently interpret a wide variety of NBTI experiments [1,[5][6][7][20][21][22][23][24]. In addition, many groups have used different variants of the R-D model in process qualification [1,6,25,26] and circuit design [26,27]. In practice, depending on the experimental conditions and the type of dielectrics, measured NBTI statistics can have contributions from both interface defects and hole-trapping into oxide defects [5-7, 22, 23, 28].…”

Section: Temporal Distribution Of Interface Defectmentioning

confidence: 99%

Analyzing the distribution of threshold voltage degradation in nanoscale transistors by using reaction-diffusion and percolation theory

Islam

Alam

2011

J Comput Electron

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Continued scaling of transistors into the nanoscale regime has led to large device-to-device variation in transistor characteristics. These variations reflect differences in substrate doping, channel length, interface and/or oxide defects, etc. among various transistors. In this paper, we develop a theory for the statistical distribution of threshold voltage degradation ( V T ) due to the Negative Bias Temperature Instability (NBTI). First, we model the time dynamics of interface defects within the Reaction-Diffusion (R-D) framework and calculate the statistics of interface defect using Markov Chain Monte-Carlo method. We show that the generation and annealing of interface defects are strongly correlated and that the statistics of interface defect at a given stress time (N IT @t STS ) follows a skew-normal distribution. Second, we explore the differential effect of the spatial distribution of interface defects in nanoscale transistors pre-populated with a discrete number of randomly placed substrate dopants. We model the effect of spatial distribution of defects using a percolative network and demonstrate that the distribution of threshold voltage degradation for a single additional interface defect, i.e., V T @ N IT = 1, is exponential, with a fraction of transistors having V T ∼ 0. Finally, we obtain the statis-Electronic supplementary material The online version of this article (tics of V T @t STS by convolving the statistics of N IT @t STS with that of V T @ N IT = 1. The resultant statistics of V T @t STS compares favorably with a broad range of experiments reported in the NBTI literature.

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A Finite-Oxide Thickness-Based Analytical Model for Negative Bias Temperature Instability

Cited by 30 publications

References 43 publications

Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits

Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits

What happens when circuits grow old: Aging issues in CMOS design

Analyzing the distribution of threshold voltage degradation in nanoscale transistors by using reaction-diffusion and percolation theory

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