Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits

Abstract-Circuit degradation due to bias temperature instability (BTI) can lead to timing failures in digital circuits. We develop variable latency unit (VLU) based BTI-aware designs, with a novel scheme for multioutput hold logic implementation for VLUs. A key observation is the identification and exploitation of specific supersetting patterns in the two-dimensional space of frequency and aging of the circuit. The multioutput hold logic scheme is used in conjunction with an adaptive body bias framework to achieve high performance, allowing the design to be easily incorporated in traditional synthesis flows. As compared to conventional combinational BTI-resilience scheme, our design achieves an area reduction of 9.2%, with a significant throughput enhancement of 30.0%. §1. INTRODUCTION Bias Temperature Instability (BTI) [1], in the form of negative BTI (NBTI) in PMOS and positive BTI (PBTI) in NMOS transistors, is a significant concern in nanoscale circuits. BTI causes the transistor threshold voltage to shift over time, and the resulting increases in delay could cause a circuit to fail timing specifications as it ages.Published approaches for enhancing BTI-resiliency include transistor sizing, logic resynthesis, or postsilicon tuning. These methods are built for conventional synchronous designs, where the worstcase delay determines the clock period. This work addresses the case where the clock period is based on the notion of average-case computations rather than the worst-case computations in a circuit, an approach that leads to improved data throughput.Within the synchronous paradigm, two classes of techniques have been proposed for exploiting the average-case computations: variablelatency units [2]-[4], and error detection-correction units [5]. Our work focuses on the design of BTI-resilient circuits using variable latency units (VLUs). Unlike conventional combinational circuits that complete operations within one clock cycle, VLUs allow the computation of the combinational circuit to be completed in a variable, integer, number of clock cycles. By allowing high-probability operations to complete in a single cycle, but allowing rarer events to use multiple (typically two) cycles, the average cycle time may be shorter than that of the conventional implementation, implying that the circuit throughput for a VLU may be significantly larger.As an illustration of a VLU, consider the 6-bit ripple carry adder (RCA) shown in Figure 1, with six full adders. Assuming unit gate delays, the conventional single-cycle fixed-latency combinational circuit has a cycle time, T clk = 13 units, equal to the delay of its longest path, corresponding to a throughput, η1 = 1/13. The VLU implementation of this adder operates at a reduced cycle time, T clk < 13. For T clk = 9, assuming that all primary input signals are mutually independent and have signal probabilities of 50%, 18.75% of the input patterns violate T clk , and the VLU allows these to complete execution in two cycles. Under the 50% assumption above, each pattern is equip...

show abstract

“…Given a BTI model, we use HSPICE to precharacterize the impact of changes in V th on the delay Dg of a gate with n transistors as [8]:…”

Section: Bti Degradation Model and Delay Monotonicitymentioning

confidence: 99%

BTI-aware design using variable latency units

Gupta

Sapatnekar

2012

17th Asia and South Pacific Design Automation Conference

Self Cite

View full text Add to dashboard Cite

show abstract

“…We then set the on-time to be C = 3 years and obtain the duty cycle values Y from our logic simulations. Next, using Equation (1), we compute the ∆V th , which can then be used to obtain σ 2 (∆V th ) using Equation (2). Using Equation (3), we then obtain the error probability of a single transistor P err .…”

Section: Results and Analysismentioning

confidence: 99%

“…Furthermore, its mean µ(∆V th ) and variance σ(∆V th ) can be obtained by Equations (1) and (2). For any given CMOS device, when ∆V th > ∆V * th , digital switching fails, where the threshold value ∆V * th can be obtained through SPICE simulations.…”

Section: Bti-induced Error Probability In Cmos Switchesmentioning

confidence: 99%

“…As electronic device technology aggressively scales towards the 22-nm node, especially with the recent introduction of high-k material to avoid the gate tunneling effect, the aging-induced reliability issue will be exacerbated greatly [1,2]. As such, structural degradation in modern Complementary Metal Oxide Semiconductor (CMOS) devices can potentially accelerate, therefore resulting in hard faults at a much faster pace [3].…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, all of these mechanisms can be worsened by the high switching rate of a circuit, excess supply voltage or high operational temperature. Among all of these transistor aging mechanisms, the most prominent ones are the negative bias-temperature instability (NBTI), which affects PMOS transistors, and the positive one (PBTI), which affects NMOStransistors [1,2,5,6]. The major effect of the NBTI and PBTI is that they increase the magnitude of the transistor's threshold voltage and reduce the effective carrier mobility over time, therefore leading to a reduction in the operational reliability of the CMOS transistor.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Optimally Fortifying Logic Reliability through Criticality Ranking

et al. 2015

View full text Add to dashboard Cite

With CMOS technology aggressively scaling towards the 22-nm node, modern FPGA devices face tremendous aging-induced reliability challenges due to bias temperature instability (BTI) and hot carrier injection (HCI). This paper presents a novel anti-aging technique at the logic level that is both scalable and applicable for VLSI digital circuits implemented with FPGA devices. The key idea is to prolong the lifetime of FPGA-mapped designs by strategically elevating the V DD values of some LUTs based on their modular criticality values. Although the idea of scaling V DD in order to improve either energy efficiency or circuit reliability has been explored extensively, our study distinguishes itself by approaching this challenge through an analytical procedure, therefore being able to maximize the overall reliability of the target FPGA design by rigorously modeling the BTI-induced device reliability and optimally solving the V DD assignment problem. Specifically, we first develop a systematic framework to analytically model the reliability of an FPGA LUT (look-up table), which consists of both RAM memory bits and associated switching circuit. We also, for the first time, establish the relationship between signal transition density and a LUT's reliability in an analytical way. This key observation further motivates us to define the modular criticality as the product of signal transition density and the logic observability of each LUT. Finally, we analytically prove, for the first time, that the optimal way to improve the overall reliability of a whole FPGA device is to fortify individual LUTs according to their modular criticality. To the best of our knowledge, this work is the first to draw such a conclusion.

show abstract