A First Insight to the Thermal Dependence of the DC, Analog and RF Performance of an S/D Spacer Engineered DG-Ambipolar FET

Bhattacharjee, Abhishek; SaiKiran, M.; Dasgupta, S.

doi:10.1109/ted.2017.2740320

Cited by 16 publications

(5 citation statements)

References 20 publications

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“…What is more, by employing a hetero-gate-dielectric (HGD) structure, GHL-TFET can not only suppress the ambipolar current by increasing the tunneling barrier at the drain/channel interface, but also improve the RF performance by reducing the gate/drain capacitance. [31][32][33][34][35][36][37] TCAD simulation results show that our proposed GHL-TFET significantly enhances I ON while effectively suppressing ambipolar current and achieves better RF performance than the conventional L-TFET.…”

Section: Introductionmentioning

confidence: 95%

Ge/Si heterojunction L-shape tunnel field-effect transistors with hetero-gate-dielectric

et al. 2018

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A Ge/Si heterojunction L-shaped tunnel field-effect transistor combined with hetero-gate-dielectric (GHL-TFET) is proposed and investigated by TCAD simulation. Current-voltage characteristics, energy-band diagrams, and the distribution of the band-to-band tunneling (BTBT) generation rate of GHL-TFET are analyzed. In addition, the effect of the vertical channel width on the ON-current is studied and the thickness of the gate dielectric is optimized for better suppression of ambipolar current. Moreover, analog/RF figure-of-merits of GHL-TFET are also investigated in terms of the cut-off frequency and gain bandwidth production. Simulation results indicate that the ON-current of GHL-TFET is increased by about three orders of magnitude compared with that of the conventional L-shaped TFET. Besides, the introduction of the hetero-gate-dielectric not only suppresses the ambipolar current effectively but also improves the analog/RF performance drastically. It is demonstrated that the maximum cut-off frequency of GHL-TFET is about 160 GHz, which is 20 times higher than that of the conventional L-shaped TFET.

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Section: Introductionmentioning

confidence: 95%

Ge/Si heterojunction L-shape tunnel field-effect transistors with hetero-gate-dielectric

et al. 2018

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“…The semiconductor industry, driven by major players like Intel and TSMC, has witnessed the transition to 5 nm chip production since mid-2020. Despite this advancement, the pursuit of further optimization in VLSI circuits persists, focusing on power consumption, operating speed, and chip area reduction [1][2][3][4][5][6][7][8][9][10][11][12]. This objective becomes increasingly critical as we continue scaling into the 'More than Moore' era, [13][14][15][16][17][18][19][20][21] aiming to uphold performance while managing power requirements.…”

Section: Introductionmentioning

confidence: 99%

A novel high-performance TG-based SRAM cell with 5 nm FinFET technology

Pal,

Upadhyaya,

Majumder

et al. 2024

Eng. Res. Express

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In this study, we investigate the performance and reliability of a novel static random-access memory (SRAM) cell utilizing advanced 5 nm FinFET technology. Our research aims to address critical challenges in SRAM design by integrating transmission gates and power gated transistors. Through extensive simulations using the Cadence Virtuoso tool, we optimize the SRAM cell’s read and write paths, resulting in substantial improvements in both functionalities. Additionally, our study unveils temperature-dependent variations in the read current and write margin, emphasizing the influence of temperature on SRAM performance. Compared to conventional FinFET SRAM circuits of equivalent bit-cell area and read latency, our innovative design showcases remarkable improvements across various parameters. Specifically, we achieve a commendable increase of 6.16% in the write static noise margin (WSNM) and 5.86% in the hold static noise margin (HSNM). Moreover, our findings reveal a substantial boost in read stability, increasing from 14.75% to 18.35%. These advancements underscore the promising potential of our approach in paving the way for future innovations in high-performance memory architectures. By leveraging state-of-the-art technology and meticulous optimization techniques, our research sets a new standard for SRAM design, offering enhanced performance, reliability, and efficiency in memory systems.

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“…Research is also going on to lessen the number of transistors in a SRAM cell to reduce the overall functional area of the chip. In earlier works from our group [10][11][12][13][14], we have shown the effectiveness of reconfigurable field effect transistors which are capable in designing complex circuits including SRAMS with lesser number of transistors as compared to conventional CMOS [15][16][17]. In this work, we introduce a novel SRAM configuration called 8T2M NVSRAM.…”

Section: Introductionmentioning

confidence: 99%

A novel MTCMOS based 8T2M NVSRAM design for low power applications with high temperature endurance

Chakraborty,

Majumder,

Debbarma

et al. 2024

Semicond. Sci. Technol.

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This research investigates, for the first time, a novel eight-transistor-two-memristor (8T2M) nonvolatile static random access memory (NVSRAM) with 7-nm technology. The key innovation in this design lies in the incorporation of multiple-threshold complementary metal oxide semiconductor (MTCMOS) technology with power gating technique, which enables efficient power management and enhanced performance with low leakage current. The implementation of multiple threshold voltage levels allows for dynamic control of transistor behavior, optimizing power consumption and read/write speeds. As compared to a traditional six-transistor (6T) static random access memory (SRAM) cell, it has been ascertained that there is a 33% enhancement in the read margin and an 18% improvement in the write margin. Moreover, the delay for read, write ‘0’ and write ‘1’ is also minimized by 63.89%, 37.99% and 42.77%. Furthermore, the power attenuation is also reduced for read and write by 63.02% and 81.6%, respectively with respect to a conventional SRAM.

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A First Insight to the Thermal Dependence of the DC, Analog and RF Performance of an S/D Spacer Engineered DG-Ambipolar FET

Cited by 16 publications

References 20 publications

Ge/Si heterojunction L-shape tunnel field-effect transistors with hetero-gate-dielectric

Ge/Si heterojunction L-shape tunnel field-effect transistors with hetero-gate-dielectric

A novel high-performance TG-based SRAM cell with 5 nm FinFET technology

A novel MTCMOS based 8T2M NVSRAM design for low power applications with high temperature endurance

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