A first-order mechanistic model for architectural vulnerability factor

Abstract

Soft error reliability has become a first-order design criterion for modern microprocessors. Architectural Vulnerability Factor (AVF) modeling is often used to capture the probability that a radiation-induced fault in a hardware structure will manifest as an error at the program output. AVF estimation requires detailed microarchitectural simulations which are time-consuming and typically present aggregate metrics. Moreover, it requires a large number of simulations to derive insight into the impact of microarchitectural events on AVF. In this work we present a first-order mechanistic analytical model for computing AVF by estimating the occupancy of correct-path state in important microarchitecture structures through inexpensive profiling. We show that the model estimates the AVF for the reorder buffer, issue queue, load and store queue, and functional units in a 4-wide issue machine with a mean absolute error of less than 0.07. The model is constructed from the first principles of out-of-order processor execution in order to provide novel insight into the interaction of the workload with the microarchitecture to determine AVF. We demonstrate that the model can be used to perform design space explorations to understand trade-offs between soft error rate and performance, to study the impact of scaling of microarchitectural structures on AVF and performance, and to characterize workloads for AVF.

Optimizing Soft Error Reliability Through Scheduling on Heterogeneous Multicore Processors

“…Nops and wrong-path instructions are assumed to be non-ACE. Table 2 shows the configurations of the big out-of-order and the small in-order core types, as well as the bit counts per entry in each structure (taken from Nair et al [22]). Note that we assume the same cache hierarchy for the small and big cores; however, in Section 10 where we focus on L1 cache vulnerability, we will vary the cache size of the small core to study the sensitivity to the cache hierarchy.…”

“…Sridharan and Kaeli [42] propose to split AVF into PVF (program vulnerability factor) and HVF (hardware vulnerability factor), which can be determined independently. Other prior work models AVF through regression on performance counters [43], [44], or through analytical mechanistic modeling [22]. Nair et al [45] develop a methodology for creating AVF-stressing benchmarks, providing a processor AVF upper bound.…”

Versatile architecture-level fault injection framework for reliability evaluation: A first report

“…[42] [23] Arch. injection [9] [41] [30] ACE analysis [26] [27] Probabilistic models [20] In this paper, we propose a comprehensive architecturelevel fault injection framework for early reliability estimation of x86 microprocessors. The proposed framework:…”

Online mechanism for reliability and power-efficiency management of a dynamically reconfigurable core

“…Prior research has shown that AVF varies at instruction granularities within applications [15]. AVF sensitivity to microarchitectural resource sizes was studied in [16]. These studies demonstrate that AVF varies from workload to workload and for a given workload, it varies from one CCM to another.…”