A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures

Liu, Leibo; Wu, Chang; Deng, Chenchen; Yin, Shouyi; Wu, Qinghua; Han, Jie; Wei, Shaojun

doi:10.1109/tvlsi.2014.2367108

Cited by 22 publications

(18 citation statements)

References 34 publications

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“…Some studies are done to optimise one metric (reliability, communication energy, temperature or performance) [5][6][7][8][9][10]. Some studies are done to optimise two or three metrics [2,11,12]. Since the manual exploration of a potentially huge design space is infeasible even for small systems, there is a number of algorithmic approaches that can be used to automate the design space exploration to optimise the NoC design.…”

Section: Introductionmentioning

confidence: 99%

Unified multi‐objective mapping for network‐on‐chip using genetic‐based hyper‐heuristic algorithms

Liu

Yang

2018

IET Computers & Digital Techniques

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In this study, a flexible energy-and delay-aware mapping approach is proposed for the co-optimisation of energy consumption and communication latency for network-on-chips (NoCs). A novel genetic-based hyper-heuristic algorithm (GHA) is proposed as the core algorithm. This algorithm consists of bottom-level optimisation which includes a variety of operators and top-level optimisation which selects suitable operators through a 'reward' mechanism. As this algorithm can select suitable operators automatically during the mapping process, it noticeably improves convergence speed and demonstrates excellent stability. Compared to the random algorithm, GHA can achieve on average 23.28% delay reduction and 11.81% power reduction. Compared to state-of-the-art mapping algorithms, GHA produces improved mapping results with less time, especially when the size of NoC is large.

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Section: Introductionmentioning

confidence: 99%

Unified multi‐objective mapping for network‐on‐chip using genetic‐based hyper‐heuristic algorithms

Liu

Yang

2018

IET Computers & Digital Techniques

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“…However, to the best of our knowledge, very few publications can be found in the literature that address the issue of fault-tolerant application mapping in NoC. As reported by [2], energy and reliable aware application mapping approach proposes a cost model by combining energy and reliability. In this work it was observed that branch-and bound-based mapping technique for regular topologies has been used.…”

Section: Related Workmentioning

confidence: 99%

Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement

Bhanu

Kulkarni

Soumya

et al. 2018

2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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The increase in the density of the IP cores being fabricated on a chip poses on-chip communication challenges and heat dissipation. To overcome these issues, Network-on-Chip (NoC) based communication architecture is introduced. In the nanoscale era NoCs are prone to faults which results in performance degradation and un-reliability. Hence efficient fault-tolerant methods are required to make the system reliable in contrast to diverse component failures. This paper presents a flexible spare core placement in torus topology based faulttolerant NoC design. The communications related to the failed core is taken care by selecting the best position for a spare core in the torus network. By considering this we propose a metaheuristic based Particle Swarm Optimization (PSO) technique to find suitable position for the spare core that minimizes the communication cost. We have experimented with several application benchmarks reported in the literature by varying the network size and by varying the fault-percentage in the network. The results show significant reduction in terms of communication cost compared to other approaches reported in literature.

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“…The works in [26,40], utilize Branch and Bound based algorithms to perform application mapping on reconfigurable many-core NoCs, where the configuration of PEs functions and interconnections is adjusted dynamically. Mapping decisions are centralized and the optimization objectives take into account reliability, energy and performance.…”

Section: Related Workmentioning

confidence: 99%

“…Fault and lifetime aware application mapping [14,26,40] is a first level of dependability extension. Proceeding to system level, fault tolerance is either achieved via centralized decision making [6,18,32] or via hierarchical designs which rely on spare PEs provisioning [9,13,21,38].…”

Section: Introductionmentioning

confidence: 99%

SoftRM

Tsoutsouras

Masouros

Xydis

et al. 2017

ACM Trans. Embed. Comput. Syst.

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Many-core systems are envisioned to leverage the ever-increasing demand for more powerful computing systems. To provide the necessary computing power, the number of Processing Elements integrated onchip increases and NoC based infrastructures are adopted to address the interconnection scalability. The advent of these new architectures surfaces the need for more sophisticated, distributed resource management paradigms, which in addition to the extreme integration scaling, make the new systems more prone to errors manifested both at hardware and software. In this work, we highlight the need for Run-Time Resource management to be enhanced with fault tolerance features and propose SoftRM, a resource management framework which can dynamically adapt to permanent failures in a self-organized, workload-aware manner. Self-organization allows the resource management agents to recover from a failure in a coordinated way by electing a new agent to replace the failed one, while workload awareness optimizes this choice according to the status of each core. We evaluate the proposed framework on Intel Single-chip Cloud Computer (SCC), a NoC based many-core system and customize it to achieve minimum interference on the resource allocation process. We showcase that its workload-aware features manage to utilize free resources in more that 90% of the conducted experiments. Comparison with relevant state-of-the-art fault tolerant frameworks shows decrease of up to 67% in the imposed overhead on application execution. CCS Concepts: • General and reference → Cross-computing tools and techniques; • Computer systems organization → Multicore architectures; • Networks → Network on chip; • Computing methodologies → Self-organization;

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A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures

Cited by 22 publications

References 34 publications

Unified multi‐objective mapping for network‐on‐chip using genetic‐based hyper‐heuristic algorithms

Unified multi‐objective mapping for network‐on‐chip using genetic‐based hyper‐heuristic algorithms

Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement

SoftRM

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