A flexible global readout architecture for an analogue SIMD vision chip

Dudek, Piotr

doi:10.1109/iscas.2003.1205136

Cited by 17 publications

(6 citation statements)

References 7 publications

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“…For example, when a SCAMP algorithm makes a request to send data to the host, the System Controller intervenes, takes control over the SCAMP chip and acquires the relevant data. The System Controller can perform flexible read-out of the array [7] either by scanning the array to access individual pixels or by defining regions of pixels. Different operations can be performed on selected regions, such as summation of array values, or performing digital OR operations.…”

Section: Scamp System Diagrammentioning

confidence: 99%

A Control System for a Cellular Processor Array

Barr

Carey

Lopich³

et al. 2006

2006 10th International Workshop on Cellular Neural Networks and Their Applications

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-Presented in this paper is a system that controls the SCAMP-3 cellular processor array vision chip, and provides an interface between it and a host system. This system can be used in real-time image processing, or computer vision applications. The system includes a sequencer for issuing instructions to the array processor, a configurable analogue interface and read-out circuitry, a system controller, which enables system operation and communication with the host, and a suite of software components, which include libraries, simulator, compiler and user interface. The presented hardware is a stand-alone vision system, which can be used in the development of PC-based or embedded applications.

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Section: Scamp System Diagrammentioning

confidence: 99%

A Control System for a Cellular Processor Array

Barr

Carey

Lopich³

et al. 2006

2006 10th International Workshop on Cellular Neural Networks and Their Applications

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“…In particular, digital [1], [2] and analog [3], [4] processor arrays have been demonstrated which not only exploit the fine-grain parallelism of the algorithms, assigning a processing element to each single pixel in the image, but also integrate image sensors for parallel optical image input. Ideally, such "smart sensors" should perform some medium-level image processing algorithms as well, so that the amount of data transmitted off-chip is significantly reduced [5], [6]. This involves the transition from pixel-wise local operations to global (e.g., object-based) operations.…”

Section: Introductionmentioning

confidence: 99%

An asynchronous cellular logic network for trigger-wave image processing on fine-grain massively parallel arrays

Dudek

2006

IEEE Trans. Circuits Syst. II

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Abstract-Massively parallel processor-per-pixel single-instruction multiple data arrays are being successfully used for early vision applications in smart sensor systems; however, they are inherently inefficient when executing algorithms involving propagation of binary signals, such as the geodesic reconstruction. Yet, these algorithms, at the interface between pixel-level and object-level image processing, should be implemented on the vision chip to facilitate data reduction at the sensor level. A cellular asynchronous network is presented in this paper, which can be used to execute binary propagation operations. The proposed circuit is optimized in terms of speed and power consumption. In 0.35-m technology, the simulated propagation speed is 0.18 ns per pixel and the total energy expended per propagation is 0.37 pJ per cell. In this brief, implementation issues are discussed and simulation results including image processing examples are presented.

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“…During grey-scale read-out the value of the output current from an analogue register is routed to the chip I/O pin, it is converted to a digital value using an external A/D converter. A flexible global readout architecture [6] permits addressing groups of APEs in the array, to facilitate global operations. This is simply implemented using address decoder similar to the one shown in Figure 5.…”

Section: Control and Readoutmentioning

confidence: 99%

“…The design is based on the design used in our previous 39×48 array chip, which has been reported in [4]. Some details of the processing element design and readout architecture were presented in [5] and [6]. In this paper, several aspects of the chip implementation are elaborated.…”

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confidence: 99%

Implementation of SIMD Vision Chip with 128X128 Array of Analogue Processing Elements

Dudek

2005 IEEE International Symposium on Circuits and Systems

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This paper presents the latest implementation of the SIMD Current-mode Analogue Matrix Processor architecture. The SCAMP-3 vision chip has been fabricated in a 0.35µm CMOS technology and comprises a 128×128 general-purpose programmable processor-perpixel array. The architecture of the chip is overviewed and implementation issues are considered. The circuit design of the analogue register is presented, the layout of the Analogue Processing Element is discussed and the design of control-signal drivers and readout circuitry is overviewed. INTRODUCTIONProgrammable vision chips, which combine image sensors and pixel-parallel processors, can offer significant advantages in many computer vision applications, providing image pre-processing capability with low power consumption and high computational performance. Inherently parallel low-level image processing algorithms map naturally to fine-grained pixel-parallel processor arrays, while the ability to perform computations right next to the sensors reduces the power consumption and I/O bandwidth requirements. However, the requirement of physically co-locating photosensor array and processor array, in a processor-perpixel manner, introduces severe constraints in terms of the physical design of the device, circuit area, and power consumption. This is especially true if a low-cost requirement implies the use of a standard CMOS technology. To meet the implementation constraints, mixed-mode and analogue circuits are usually employed in the design of the processor. It has been demonstrated [1-3] that use of analogue processors can offer significant benefits in terms of cost, processing speed and power consumption, when limited accuracy of processing is acceptable. The implementation of a large analogue VLSI circuit, however, is a challenging task. The trade-offs between cell area, power dissipation and processing speed have to be suitably resolved. A full-custom design is obviously required, and the constraints on the physical geometry of the circuit topology are an important consideration affecting the circuit and system design. This implies a co-design of processor architecture, circuitry and layout. Furthermore, to achieve a robust implementation, the issues of noise and mismatch have to be carefully controlled. Again, the architecture and physical design have to be considered together.In this paper the design of a 128×128 pixel-perprocessor vision chip (SCAMP-3, shown in Figure 1) is presented. The chip has been fabricated in a 0.35µm CMOS technology and comprises over 1.8 million transistors (most of which are working in analogue mode). The design is based on the design used in our previous 39×48 array chip, which has been reported in [4]. Some details of the processing element design and readout architecture were presented in [5] and [6]. In this paper, several aspects of the chip implementation are elaborated. In particular, detailed schematic diagram of the analogue register circuit is presented, the layout of the processing element is discussed and the control...

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A flexible global readout architecture for an analogue SIMD vision chip

Cited by 17 publications

References 7 publications

A Control System for a Cellular Processor Array

A Control System for a Cellular Processor Array

An asynchronous cellular logic network for trigger-wave image processing on fine-grain massively parallel arrays

Implementation of SIMD Vision Chip with 128X128 Array of Analogue Processing Elements

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