Implementation of SIMD Vision Chip with 128X128 Array of Analogue Processing Elements

Abstract

This paper presents the latest implementation of the SIMD Current-mode Analogue Matrix Processor architecture. The SCAMP-3 vision chip has been fabricated in a 0.35µm CMOS technology and comprises a 128×128 general-purpose programmable processor-perpixel array. The architecture of the chip is overviewed and implementation issues are considered. The circuit design of the analogue register is presented, the layout of the Analogue Processing Element is discussed and the design of control-signal drivers and readout circuitry is overviewed. INTRODUCTIONProgrammable vision chips, which combine image sensors and pixel-parallel processors, can offer significant advantages in many computer vision applications, providing image pre-processing capability with low power consumption and high computational performance. Inherently parallel low-level image processing algorithms map naturally to fine-grained pixel-parallel processor arrays, while the ability to perform computations right next to the sensors reduces the power consumption and I/O bandwidth requirements. However, the requirement of physically co-locating photosensor array and processor array, in a processor-perpixel manner, introduces severe constraints in terms of the physical design of the device, circuit area, and power consumption. This is especially true if a low-cost requirement implies the use of a standard CMOS technology. To meet the implementation constraints, mixed-mode and analogue circuits are usually employed in the design of the processor. It has been demonstrated [1-3] that use of analogue processors can offer significant benefits in terms of cost, processing speed and power consumption, when limited accuracy of processing is acceptable. The implementation of a large analogue VLSI circuit, however, is a challenging task. The trade-offs between cell area, power dissipation and processing speed have to be suitably resolved. A full-custom design is obviously required, and the constraints on the physical geometry of the circuit topology are an important consideration affecting the circuit and system design. This implies a co-design of processor architecture, circuitry and layout. Furthermore, to achieve a robust implementation, the issues of noise and mismatch have to be carefully controlled. Again, the architecture and physical design have to be considered together.In this paper the design of a 128×128 pixel-perprocessor vision chip (SCAMP-3, shown in Figure 1) is presented. The chip has been fabricated in a 0.35µm CMOS technology and comprises over 1.8 million transistors (most of which are working in analogue mode). The design is based on the design used in our previous 39×48 array chip, which has been reported in [4]. Some details of the processing element design and readout architecture were presented in [5] and [6]. In this paper, several aspects of the chip implementation are elaborated. In particular, detailed schematic diagram of the analogue register circuit is presented, the layout of the processing element is discussed and the control...

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“…The SCAMP-3 Vision Chip prototype [28] is a 128 × 128 px cellular processor array. It includes a processorper-pixel in a mixed-mode architecture.…”

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“…on the CNN-paradigm [1] or somewhat different but still massively parallel and locally connected processing [2], [3], [4], [5] offer great performance advantages compared to traditional sequential processing architectures. These advantages are especially apparent in image processing applications.…”

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“…The SCAMP-3 vision chip [6] is a 128x128 cellular processor array. The array consists of 16,384 analogue processing elements (APE), each coupled with a photo-sensor that captures light focused onto the array.…”