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The most common values for p are p=l (Sum of Absolute DifferAn evolved version of variable block-size analog motion estimation ences, SAD) and p=2 (Sum of Squared Differences, SSD). In AME, cell structure is presented. Due to the space restrictions of interconnects, the SSD is known to be superior to the SAD. However, due to used advanced variable block-size motion estimation architecture necesi sitates using deep-submicron design technology, which enables the dense its efficient digital implementation the SAD is the most often used spacing of interconnects. Therefore, a novel architecture realizing the cell matching criterion. The ME process can be broken into three basic structure in modern 130 nm operations:technology and being more robust against analog inaccuracies than 1) Shift of reference pixel (reference block) data ref (i2, j2) previous implementations, is designed and simulated. ref(i + dx,j + dy).

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We present a novel combination selection counter structure for effective search in Gaussian distribution applications. The proposed structure is designed to be used in certain mismatch compensation circuit. However, it can be also used in other applications, where some bit combinations are more probable than others. This counter enables remarkable savings in the switching activity of the calibration stages. In combination selection, the proposed counter enables on average 17 % lower switching activity, than traditional Gray counter. The effect of lower switching is emphasized when the counter is used in large array structures with high coupling capacitances.

A combination selection based device mismatch calibration for mixed-mode array processors is discussed. Clear benefits in implementation area and accuracy, compared to large transistors can be reached by using mismatch calibration which is based on the combination selection of minimum-sized transistors. By utilizing the in-cell memory elements present in a mixed-mode array processor in the compensation, the area benefits can be further significantly increased.Two separate calibration cases are discussed in this paper. In the first case, a structure for mismatch calibration in current references is examined. In the second case, a structure for calibrating mismatch and linearity errors in current mirrors is proposed. All structures in the paper have been designed and simulated using 90 nm digital CMOS technology.