Current mismatch and nonlinearity compensation in mixed-mode array processors

Abstract

A combination selection based device mismatch calibration for mixed-mode array processors is discussed. Clear benefits in implementation area and accuracy, compared to large transistors can be reached by using mismatch calibration which is based on the combination selection of minimum-sized transistors. By utilizing the in-cell memory elements present in a mixed-mode array processor in the compensation, the area benefits can be further significantly increased.Two separate calibration cases are discussed in this paper. In the first case, a structure for mismatch calibration in current references is examined. In the second case, a structure for calibrating mismatch and linearity errors in current mirrors is proposed. All structures in the paper have been designed and simulated using 90 nm digital CMOS technology.

An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation

“…Also, because the whole image cannot be practically processed with the array at the same time, also the speed of operation should be maximized by targeting the smallest possible capacitive loads, that is, smallest possible transistors. In this respect the application of area-efficient mismatch compensation techniques in the AME cell, such as the one discussed in [14], should be considered.…”