Interconnect-efficient reference data shift for optimized analog motion estimation

Poikonen, Jonne; Laiho, Mika; Paasio, A.; Koskinen, Lauri; Halonen, K.

doi:10.1109/cnna.2008.4588658

Cited by 2 publications

(2 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The proposed shift implementation leads to a significant reduction in the required cell interconnections, enabling a [8,8] cell search range to be implemented with a simpler array-level wiring than in previous implementations and with simple controllability. This paper extends the original paper proposing the new reference-shift method [9], by also describing in detail the implementation of other circuitry for the array cell as well as presenting the implementation of a 32×32 cell AME test chip that has been designed and submitted for manufacturing. The paper is divided into seven Sections.…”

Section: Introductionmentioning

confidence: 86%

An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation

Poikonen

Laiho

Paasio

et al. 2009

EURASIP J. Adv. Signal Process.

Self Cite

View full text Add to dashboard Cite

A cellular analog processor array for use in variable block-size motion estimation with a new simple method for shifting reference image data is presented. The new shift method leads to a greatly reduced number of neighborhood connections for each cell of the array, and allows for all shifts within the [8,8] search area to be performed in a single step, with simple digital controls. The new shift circuitry, together with some other cell and system level optimizations , reduces silicon area and array layout complexity, enabling faster and more efficient parallel full search motion estimation hardware. A 32 × 32 cell parallel analog test array for reference-shift with a maximum block-size of 16 × 16, as well as absolute value/quadratic processing for variable block-size analog motion estimation (AME) has been designed in a 0.13 μm CMOS technology.

show abstract

Section: Introductionmentioning

confidence: 86%

An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation

Poikonen

Laiho

Paasio

et al. 2009

EURASIP J. Adv. Signal Process.

Self Cite

View full text Add to dashboard Cite

show abstract

“…mirrors used for an incell binary-output current comparator with a variable threshold value or the input section of analog processing circuitry, where current mirroring operations may be required just to change the direction of the input current for certain processing blocks. Also, in a CNN-type implementation of analog motion estimation [10], the only source of device mismatch in a reference image shift operation is a single current mirror, which would be a natural target for compensation. To optimize the method originally designed for fixed current reference calibration, some modifications have been made.…”

Section: A Ideamentioning

confidence: 99%

Current mismatch and nonlinearity compensation in mixed-mode array processors

Marku

Virtanen

Maunu

et al. 2008

2008 11th International Workshop on Cellular Neural Networks and Their Applications

Self Cite

View full text Add to dashboard Cite

A combination selection based device mismatch calibration for mixed-mode array processors is discussed. Clear benefits in implementation area and accuracy, compared to large transistors can be reached by using mismatch calibration which is based on the combination selection of minimum-sized transistors. By utilizing the in-cell memory elements present in a mixed-mode array processor in the compensation, the area benefits can be further significantly increased.Two separate calibration cases are discussed in this paper. In the first case, a structure for mismatch calibration in current references is examined. In the second case, a structure for calibrating mismatch and linearity errors in current mirrors is proposed. All structures in the paper have been designed and simulated using 90 nm digital CMOS technology.

show abstract

Interconnect-efficient reference data shift for optimized analog motion estimation

Cited by 2 publications

References 9 publications

An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation

An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation

Current mismatch and nonlinearity compensation in mixed-mode array processors

Contact Info

Product

Resources

About