A Flexible Hardware Encoder for Low-Density Parity-Check Codes

A real time programmable encoder for low density parity check code targeting a reconfigurable instruction cell architecture

“…For other code rates like 3/4 and using the same frame size, the execution time per information bit came out to be 52.63 nsec which resulted in 19 Mbps throughput. An FPGA implementation [8] provides 22Mbps (13% more) but is not real time programmable and does not provide the flexibility that the cell based reconfigurable architecture is offering for implementation from C/C++.…”

“…The processing in each block is similar to the processing defined in [8]. Here MVM is the matrix-vector-multiplication with a vector output.…”

“…This huge memory storage requirement can be reduced by adopting the methodology in [8] for storing the child matrices. Since H is sparse regarding number of 1's, a huge memory reduction is possible if only the indexes of 1's in the H matrix or the child matrices are stored.…”

“…If the indexes of only the 1's in the H matrix are stored then only 8Kwords or 16Kbytes of memory is needed instead of 316Kbytes which is equivalent to a reduction of about 20 times in memory. The authors in [8] have stored the indexes of only 1's in the child matrices. Each child matrix is accompanied by another array which stores a '1' for the index of H and '0' for the end of the row.…”