A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis

Chakraborty, Rajat Subhra; Pagliarini, Samuel; Mathew, Jimson; Rajendran, Sree Ranjani; Devi, M. Nirmala

doi:10.1109/tetc.2017.2654268

Cited by 41 publications

(9 citation statements)

References 37 publications

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“…Hardware Trojan Counteracts: the methods are categorized as: (1) Detections [100]- [102], (2) Design for security [103]- [105], and (3) Runtime monitoring [106]- [107]. Detection is the technique that determines whether a trojan exists in a piece of IC.…”

Section: Watermarkingmentioning

confidence: 99%

S⁴oC: A Self-Optimizing, Self-Adapting Secure System-on-Chip Design Framework to Tackle Unknown Threats — A Network Theoretic, Learning Approach

Nazarian

Bogdan

2020

2020 IEEE International Symposium on Circuits and Systems (ISCAS)

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We propose a framework for the design and optimization of a secure self-optimizing, self-adapting system-onchip (S 4 oC) architecture. The goal is to minimize the impact of attacks such as hardware Trojan and side-channel, by making real-time adjustments. S 4 oC learns to reconfigure itself, subject to various security measures and attacks, some of which possibly unknown at design time. Furthermore, the data types and patterns of the target applications, environmental conditions, and sources of variations are incorporated. S 4 oC is a manycore system, modeled as a four-layer graph, representing the model of computation (MoCp), model of connection (MoCn), model of memory (MoM) and model of storage (MoS), with a large number of elements including heterogeneous reconfigurable processing elements in MoCp, and memory elements in the MoM layer. Security driven community detection, and neural networks are utilized for application task clustering, and distributed reinforcement learning (RL) for task mapping.

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Section: Watermarkingmentioning

confidence: 99%

S⁴oC: A Self-Optimizing, Self-Adapting Secure System-on-Chip Design Framework to Tackle Unknown Threats — A Network Theoretic, Learning Approach

Nazarian

Bogdan

2020

2020 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Trojans of small sizes can effectively "hide" in the margins of the fabrication process. The same way antivirus detection routines has evolved from simple static checks to signature-less approaches, trojan detection has also shifted to dynamic approaches like concurrent execution and (self-)checking [13]. Other attacks that target hardware take different forms.…”

Section: Re-imagining Software Threats and Defencesmentioning

confidence: 99%

Latest Trends in Hardware Security and Privacy

2020

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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In the last two decades we have witnessed a massive development of technologies (both hardware and software) which have enabled the creation of billions of connected devices. These devices are nowadays used in a very wide range of applications, and they all contain different types of valuable assets, which have been the target of an increasing number of cyber attacks. Both scientific and industrial communities have focused their attention to implement new design processes to reduce the risk of cybersecurity breaches. This paper includes two different contributions in the field of hardware security and privacy.

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“…However, Chakraborty and Pagliarini [32] proved that when the Trojan triggers probability is less than 10 −3 , MERO will be difficult to detect Trojans.…”

Section: B Circuit Feature Analysismentioning

confidence: 99%

A Multi-Layer Hardware Trojan Protection Framework for IoT Chips

Dong

Liu

et al. 2019

IEEE Access

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Since integrated circuits are performed by several untrusted manufacturers, malicious circuits (hardware Trojans) can be implanted in any stage of the Internet-of-Things (IoT) devices. With the globalization of the IoT device manufacturing technologies, protecting the system-on-chip (SoC) security is always the keys issue for scientists and IC manufacturers. The existing SoC high-level synthesis approaches cannot guarantee both register-transfer-level and gate-level security, such as some formal verification and circuit characteristic analysis technologies. Based on the structural characteristics of hardware Trojans, we propose a multi-layer hardware Trojan protection framework for the Internet-of-Things perception layer called RG-Secure, which combines the third-party intellectual property trusted design strategy with the scan-chain netlist feature analysis technology. Especially at the gate level of chip design, our RG-Secure is equipped with a distributed, lightweight gradient lifting algorithm called lightGBM. The algorithm can quickly process high-dimensional circuit feature information and effectively improve the detection efficiency of hardware Trojans. In the meanwhile, a common evaluation index F-measure is used to prove the effectiveness of our method. The experiments show that RG-Secure framework can simultaneously detect register-transfer-level and gate-level hardware Trojans. For the trust-HUB benchmarks, the optimized lightGBM classifier achieves up to 100% true positive rate and 94% true negative rate; furthermore, it achieves 99.8% average F-measure and 99% accuracy, which shows a promising approach to ensure security during the design stage. INDEX TERMS Internet of Things, protection framework, hardware security, hardware Trojan.

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A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis

Cited by 41 publications

References 37 publications

S⁴oC: A Self-Optimizing, Self-Adapting Secure System-on-Chip Design Framework to Tackle Unknown Threats — A Network Theoretic, Learning Approach

S⁴oC: A Self-Optimizing, Self-Adapting Secure System-on-Chip Design Framework to Tackle Unknown Threats — A Network Theoretic, Learning Approach

Latest Trends in Hardware Security and Privacy

A Multi-Layer Hardware Trojan Protection Framework for IoT Chips

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A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis

Cited by 41 publications

References 37 publications

S4oC: A Self-Optimizing, Self-Adapting Secure System-on-Chip Design Framework to Tackle Unknown Threats — A Network Theoretic, Learning Approach

S4oC: A Self-Optimizing, Self-Adapting Secure System-on-Chip Design Framework to Tackle Unknown Threats — A Network Theoretic, Learning Approach

Latest Trends in Hardware Security and Privacy

A Multi-Layer Hardware Trojan Protection Framework for IoT Chips

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Product

Resources

About

S⁴oC: A Self-Optimizing, Self-Adapting Secure System-on-Chip Design Framework to Tackle Unknown Threats — A Network Theoretic, Learning Approach

S⁴oC: A Self-Optimizing, Self-Adapting Secure System-on-Chip Design Framework to Tackle Unknown Threats — A Network Theoretic, Learning Approach