A Flip-Syndrome-List Polar Decoder Architecture for Ultra-Low-Latency Communications

Abstract

We consider practical hardware implementation of Polar decoders. To reduce latency due to the serial nature of successive cancellation (SC), existing optimizations [7]- [13] improve parallelism with two approaches, i.e., multi-bit decision or reduced path splitting. In this paper, we combine the two procedures into one with an error-pattern-based architecture. It simultaneously generates a set of candidate paths for multiple bits with pre-stored patterns. For rate-1 (R1) or single parity-check (SPC) nodes, we prove that a small number of deterministic patterns are required to guarantee performance preservation. For general nodes, low-weight error patterns are indexed by syndrome in a look-up table and retrieved in O(1) time. The proposed flip-syndrome-list (FSL) decoder fully parallelizes all constituent code blocks without sacrificing performance, thus is suitable for ultra-low-latency applications. Meanwhile, two code construction optimizations are presented to further reduce complexity and improve performance, respectively.

A unified polar decoder platform for low-power and low-cost devices

“…Both SC and SCL decoders can benefit from a series of multi-bit decision techniques to prune certain decoding tree branches. Readers may refer to [6] [8] [9] [10] for several wellknown multi-bit decision techniques for SC decoding, and [11] [12] [13] for SCL decoding. Thanks to these techniques, a none-leaf node can become a bit-decision node because its child leaf nodes no longer need to be visited.…”

“…2) Adaptive SC and SCL8T8-serial decoder: Besides the modules in SC, an SCL decoder also includes additional multibit decision modules to support flip-syndrome algorithm at stage s = 2 [13], which can avoid the sorting between the candidates extended from the same path. Meanwhile, this module also supports fast decoding at nodes of v G and v F .…”

On the Construction of $G_N$-coset Codes for Parallel Decoding

“…The inner code parts consist of independent component codes that can be decoded in parallel (the j-th code bit of the i-th inner component code is denoted by x(i, j) in Fig. 1(a)) [3]. In contrast, the outer code parts must be decoded successively, which is the major source of latency of all SCbased decoding algorithms.…”