A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs

Fujiwara, Koichi; Kawamura, Kazushi; Abe, Shigenobu; Yanagisawa, Masao; Togawa, Nozomu

doi:10.1587/transfun.e98.a.1392

IEICE Trans. Fundamentals

2015

DOI: 10.1587/transfun.e98.a.1392

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A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs

Koichi Fujiwara

Kazushi Kawamura

Shigenobu Abe

et al.

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High-level synthesis for FPGAs: code optimization strategies for real-time image processing

Benezeth

et al. 2017

J Real-Time Image Proc

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High-Level Synthesis (HLS) is a potential solution to increase the productivity of FPGA based real-time image processing development. It allows designers to reap the benefits of hardware implementation directly from the algorithm behaviors specified using C-like languages with high abstraction level. In order to close the performance gap between the manual and HLS based FPGA designs, various code optimization forms are made available in today's HLS tools. This paper proposes a HLS source code and directive manipulation strategy for real-time image processing by taking into account the applying order of different optimization forms. Experiment results demonstrate that our

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High-level synthesis for FPGAs: code optimization strategies for real-time image processing

Benezeth

et al. 2017

J Real-Time Image Proc

View full text Add to dashboard Cite

show abstract

Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs

Fujiwara

Kawamura

Yanagisawa

et al. 2016

IEICE Trans. Fundamentals

View full text Add to dashboard Cite

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A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs

Cited by 2 publications

References 18 publications

High-level synthesis for FPGAs: code optimization strategies for real-time image processing

High-level synthesis for FPGAs: code optimization strategies for real-time image processing

Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs

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