A FoM of −191 dB, 4.4-GHz LC-VCO Integrating an 8-Shaped Inductor with an Orthogonal-Coupled Tail-Filtering Inductor

Fully Integrated On-Chip Inductors: An Overview

“…With utilizing special layout techniques (e.g. Horizontal Parallelization [38], Slicing [39], Tapering [40], Equal Path Lengths (EPL) [41], Patterned Ground Shield (PGS) [42], [43] and others), the inductor properties can be optimized to comply with requirements in these technologies as well [8], [20], [22]- [24]. These techniques can effectively suppress undesirable parasitic effects present in on-chip inductors caused mostly by high frequency signal (e.g.…”

“…Table II summarizes key parameters of the selected on-chip inductors implemented and published within the last 4 years. Inductors were fully integrated and evaluated by measurements except for structures in [8], [23] and [24]. These three structures were evaluated only by simulation but achieved interesting results in standard general purpose cost effective technologies without any post-CMOS process steps, where achieved values of inductance densities were L A = 150.6 nH/mm 2 , L A = 32.292 nH/mm 2 and L A = 24.015 nH/mm 2 , and the maximum quality factor (Q max ) values of 15.6, 3.1 and 6 were reported.…”

“…The performed analysis and presented overview of on-chip inductors might be very useful not only for IC research and development purposes but also in education and teaching, where curricula of different subjects on integrated circuit design can be complemented. [9] 2018 [25] 2019 [12] 2019 [4] Technology [19] 2020 [24] 1 2020 [14], [15] 2020 [26] 2020 [13] 2020 [5] 2020 [34] 2021 [8] 1 [16] 2021 [32] 2021 [17] 2021 [23] 1 2022 [52] 2022 [58] 1…”