A formal and empirical analysis of recombination for genetic algorithm-based approaches to the FPGA placement problem

Collier, Robert D.; Fobel, Christian; Richards, Laura M.; Gréwal, Gary

doi:10.1109/ccece.2012.6334856

Cited by 9 publications

(3 citation statements)

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“…FPGA placement maps a clustered logical circuit to an array of ixed physical components to optimize routing area, critical path, power eiciency, and other metrics. FPGA placement algorithms can be broadly classiied into four categories: (1) classic min-cut partitioning [32,33,46], (2) popular simulated-annealing-based methods [2,3,23,31], (3) analytical placement currently used in FPGA CAD tools [1,12,15,28], and (4) esoteric evolutionary approaches [7,20,47]. Min-cut algorithm worked well on small FPGA capacities by iteratively partitioning the circuit to spread the cells across the device.…”

Section: Fpga Placementmentioning

confidence: 99%

RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm

Zhang

Chen

Kapre

2022

ACM Trans. Reconfigurable Technol. Syst.

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Evolutionary algorithms can outperform conventional placement algorithms such as simulated annealing, analytical placement, and manual placement on runtime, wirelength, pipelining cost, and clock frequency when mapping hard block intensive designs such as systolic arrays on Xilinx UltraScale+ FPGAs. For certain hard-block intensive designs, the commercial-grade Xilinx Vivado CAD tool cannot provide legal routing solutions without tedious manual placement constraints. Instead, we formulate hard block placement as a multi-objective optimization problem that targets wirelength squared and bounding box size. We build an end-to-end placement-and-routing flow called RapidLayout using the Xilinx RapidWright framework. RapidLayout runs 5–6 × faster than Vivado with manual constraints and eliminates the weeks-long effort to manually generate placement constraints. RapidLayout outperforms (1) a tuned simulated annealer by 2.7–30.8 × in runtime while achieving similar quality of results, (2) VPR by 1.5 × in runtime, 1.9–2.4 × in wirelength, and 3–4 × in bounding box size, while also (3) beating the analytical placer UTPlaceF by 9.3 × in runtime, 1.8–2.2 × in wirelength, and 2–2.7 × in bounding box size.

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Section: Fpga Placementmentioning

confidence: 99%

RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm

Zhang

Chen

Kapre

2022

ACM Trans. Reconfigurable Technol. Syst.

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“…al. [4] [19] has found that GAs for FPGA placement are not yet comparable to SA implementations mainly due to the weakness of the crossover operator. Collier has proposed a CSR crossover operator, which they experimentally show is better than the PMX originally proposed by Goldberg for the traveling salesman problem [20].…”

Section: B Gas For Fpga Placementmentioning

confidence: 99%

Supergenes in a genetic algorithm for heterogeneous FPGA placement

Jamieson

Gharibian

Shannon

2013

2013 IEEE Congress on Evolutionary Computation

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Abstract-Supergenes are an addition to a genetic algorithm's genome that duplicate genes in the genome, represent local optimizations, and have the potential to be expressed overriding the duplicated gene. We introduce supergenes in a genetic algorithm for FPGA placement where a placement algorithm places a mix of fine-grain components and medium-grain components (where a medium-grain component is 2 to 10 times the size of a finegrain component). This is the first placement algorithm, to our knowledge, that can deal with such a mix of components on an FPGA. Our results show that supergenes improve a placement metric (clock speed of the FPGA) by approximately 10%. We also show and explore mutation operators on supergenes, and we experimentally demonstrate that the expression of a supergene can be effectively controlled via a binary function for our placement problem.

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“…Uncommon attributes of an individual may still be used to "fish-out" a person's identity, even though one may not know their name, phone number, or address explicitly from a database [4][5] [6] [7].…”

Section: A Backgroundmentioning

confidence: 99%

Anonymous Broadcast Messages

Lazić¹,

Obimbo²

2013

IJACSA

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Abstract-The Dining Cryptographer network (or DC-net) is a privacy preserving communication protocol devised by DavidChaum for anonymous message publication. A very attractive feature of DC-nets is the strength of its security, which is inherent in the protocol and is not dependent on other schemes, like encryption. Unfortunately the DC-net protocol has a level of complexity that causes it to suffer from exceptional communication overhead and implementation difficulty that precludes its use in many real-world use-cases. We have designed and created a DC-net implementation that uses a pure clientserver model, which successfully avoids much of the complexity inherent in the DC-net protocol. We describe the theory of DCnets and our pure client-server implementation, as well as the compromises that were made to reduce the protocol's level of complexity. Discussion centers around the details of our implementation of DC-net.

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A formal and empirical analysis of recombination for genetic algorithm-based approaches to the FPGA placement problem

Cited by 9 publications

References 10 publications

RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm

RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm

Supergenes in a genetic algorithm for heterogeneous FPGA placement

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