A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets

Lampka, Kai; Giannopoulou, Georgia; Pellizzoni, Rodolfo; Wu, Zheng Pei; Stoimenov, Nikolay

doi:10.1007/s11241-014-9211-y

Cited by 28 publications

(19 citation statements)

References 34 publications

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“…Yao et al (2012) presented a TDMA scheduling algorithm for PREM tasks on a multicore, and Wasly and Pellizzoni (2014) provided schedulability analysis for nonpreemptable PREM tasks on a partitioned multicore. Lampka et al (2014) proposed a formal approach for bounding the worst-case response time of concurrently executing real-time tasks under resource contention and almost arbitrarily complex resource arbitration policies, with a focus on main memory as a shared resource. Global scheduling of PREM tasks has also been considered by Alhammad and Pellizzoni (2014) and Alhammad et al (2015).…”

Section: Related Work Assuming Different Application Modelsmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on contextindependent WCET values. Instead, the analysis formulates response times directly The additional material includes: Section 4: analysis for warmed-up caches and dynamic scratchpads (Sects. 4.3 and 4.2). Section 7: extensions to the task model, including RTOS and interrupts, shared software resources, and open systems and incremental verification. Section 8: presentation of a cycle-accurate multicore simulator. Section 9: evaluation of different local memory types (Sect. 9.2), a comparison between predictable and reference architectures (Sect. 9.3), and a verification of the precision of the analysis using results from the simulator (Sect. 9.4). 123Real-Time Syst from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

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Section: Related Work Assuming Different Application Modelsmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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“…Related Work: In 2014, Lampka et al [12] proposed an approach based on timed automata and abstract interpretation.…”

Section: Rtns 2016mentioning

confidence: 99%

Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor

Rihani

Moy

Maïza

et al. 2016

Proceedings of the 24th International Conference on Real-Time Networks and Systems

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In this paper we introduce a response time analysis technique for Synchronous Data Flow programs mapped to multiple parallel dependent tasks running on a compute cluster of the Kalray MPPA-256 many-core processor. The analysis we derive computes a set of response times and release dates that respect the constraints in the task dependency graph. We extend the Multicore Response Time Analysis (MRTA) framework by deriving a mathematical model of the multilevel bus arbitration policy used by the MPPA. Further, we refine the analysis to account for the release dates and response times of co-runners, and the use of memory banks. Further improvements to the precision of the analysis were achieved by splitting each task into two sequential phases, with the majority of the memory accesses in the first phase, and a small number of writes in the second phase. Our experimental evaluation focused on an avionics case study. Using measurements from the Kalray MPPA-256 as a basis, we show that the new analysis leads to response times that are a factor of 4.15 smaller for this application, than the default approach of assuming worst-case interference on each memory access.

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“…The predictable interval (which is used with the same meaning as superblock) is also used to derive a modeling-based WCRT analysis method based on Timed Automata (TA) [49] and model checking is used for verification of the temporal properties of the system. To improve the scalability of the model checking, they also present a method that replaces parts of the model's abstract representations based on access request arrival curves [51].…”

Section: Execution Modelsmentioning

confidence: 99%

Timing Predictability in Future Multi-Core Avionics Systems

Löfwenmark¹

2017

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With more functionality added to safety-critical avionics systems, new platforms are required to offer the computational capacity needed. Multi-core platforms offer a potential that is now being explored, but they pose significant challenges with respect to predictability due to shared resources (such as memory) being accessed from several cores in parallel. Multi-core processors also suffer from higher sensitivity to permanent and transient faults due to shrinking transistor sizes.This thesis addresses several of these challenges. First, we review major contributions that assess the impact of fault tolerance on worst-case execution time of processes running on a multi-core platform. In particular, works that evaluate the timing effects using fault injection methods. We conclude that there are few works that address the intricate timing effects that appear when inter-core interferences due to simultaneous accesses of shared resources are combined with the fault tolerance techniques. We assess the applicability of the methods to COTS multi-core processors used in avionics. We identify dark spots on the research map of the joint problem of hardware reliability and timing predictability for multi-core avionics systems.Next, we argue that the memory requests issued by the real-time operating systems (RTOS) must be considered in resource-monitoring systems to ensure proper execution on all cores.We also adapt and extend an existing method for worst-case response time analysis to fulfill the specific requirements of avionics systems. We relax the requirement of private memory banks to also allow cores to share memory banks.

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A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets

Cited by 28 publications

References 34 publications

An extensible framework for multicore response time analysis

An extensible framework for multicore response time analysis

Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor

Timing Predictability in Future Multi-Core Avionics Systems

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