A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic

Hafer, Lou; Parker, Alice C.

doi:10.1109/dac.1981.1585454

Cited by 17 publications

(8 citation statements)

References 3 publications

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“…Since Hafer and Parker [10] rst proposed mixed ILP as the optimization method for datapath synthesis, numerous authors demonstrated the eectiveness of this method as a scheduling, assignment, and resource allocation tool. Notable work includes research reported in [6].…”

Section: Integer-linear Programmingmentioning

confidence: 99%

Optimal ILP-based approach for throughput optimization using simultaneous algorithm/architecture matching and retiming

DeCastelo-Vide-e-Souza¹,

Potkonjak

Parker³

1995

Proceedings of the 32nd ACM/IEEE Conference on Design Automation Conference - DAC '95

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{ System level design and behavior transformations have been rapidly establishing themselves as design steps with the most inuential impact onnal performance metrics, throughput and latency, o f a design. In this paper we develop a formal ILPbased approach for throughput and latency optimization when algorithm-architecture matching, retiming, and pipelining are considered simultaneously. The effectiveness of the approach is demonstrated on several real-life examples.

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Section: Integer-linear Programmingmentioning

confidence: 99%

Optimal ILP-based approach for throughput optimization using simultaneous algorithm/architecture matching and retiming

DeCastelo-Vide-e-Souza¹,

Potkonjak

Parker³

1995

Proceedings of the 32nd ACM/IEEE Conference on Design Automation Conference - DAC '95

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“…The minimum node firing period [4] is used as the clock cycle of the PE executing the operation of this node The data flow graph (DFG) model has been successfully used for many years for representing digital signal processing algorithms [7][8][9][10][11][12]. A DFG, or simply a graph G, can be represented by the pair (V, E), where V is a set of vertices or nodes (which represent operations) and E is a set of elements called edges (which represent data dependency) .…”

Section: Introductionmentioning

confidence: 99%

Memory Optimization on Heterogeneous Multiprocessor Embedded Systems for DSP Applications

Shatnawi

Ghanim

Swamy

2003

International Journal of Modelling and Simulation

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Embedded systems are widely used in the implementation of DSP applications. The implementation of such a system can be entirely accomplished on a single ASIC chip. An ASIC implementing a complicated DSP task is normally composed of a set of heterogeneous processing elements, an interconnection network, and memory elements. Because the type and size of the memory used have a great effect on the cost and complexity of the entire system, a memory allocation process should be optimized to reduce the memory complexity. This paper proposes a static memory allocation algorithm for synchronous heterogeneous multiprocessor integrated systems, implementing DSP applications. This allocation algorithm is designed to minimize the memory size, or alternatively, the number of registers. The proposed register allocation algorithm is shown to outperform other algorithms on all the tested benchmarks. Furthermore, two types of memory systems are introduced: central shared memory and distributed shared memory systems. The advantages and disadvantages of each memory system are also given.

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“…Hafer and Parker pioneered formulating a high-level synthesis problem into an integer linear programming (ILP) model in the early 1980s [7]. Some recent works include Gebotys and Elmasry and Rim et al [8] [9].…”

Section: Introductionmentioning

confidence: 99%

On ILP formulations for built-in self-testable data path synthesis

Kim

Takahashi

1999

Proceedings of the 36th Annual ACM/IEEE Design Automation Conference

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In this paper, we present a new method to the built-in selftestable data path synthesis based on integer linear programming (ILP). Our method performs system register assignment, built-in self-test (BIST) register assignment, and interconnection assignment concurrently to yield optimal designs. Our experimental results show that our method successfully synthesizes BIST circuits for all six circuits experimented. All the BIST circuits are better in area overhead than those generated by existing high-level BIST synthesis methods.

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A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic

Cited by 17 publications

References 3 publications

Optimal ILP-based approach for throughput optimization using simultaneous algorithm/architecture matching and retiming

Optimal ILP-based approach for throughput optimization using simultaneous algorithm/architecture matching and retiming

Memory Optimization on Heterogeneous Multiprocessor Embedded Systems for DSP Applications

On ILP formulations for built-in self-testable data path synthesis

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